STR710F Interface SRAM Problem

rlobos · ‎2007-04-16

Posted on April 17, 2007 at 06:35

rlobos · ‎2007-04-13

Posted on April 13, 2007 at 19:09

I have a STR710FZ2T6 on a Prototype board, I need use EMI to write Data on a SRAM memory 128Kx16 bits (IS62VW12816BLL-55TLI), I am using a IAR Embedded Workbench v4.0, IAR Compiler v4.31A and v4.41A. When I write data to RAM some cells are overwritted on a read instruction from strange manner that we don't understand.

I use Simulator and the routines works, but using JTAG (IAR JLINK) two cells (same cells all the time with diferent boards) are overwritted, but if I put more code the overwrite error is shifted to other cells.

I send a PDF document with conection used and a test Program. I put a breakpoint when the verify routine find a error.

Regards,

RL

________________

Attachments :

070413_EMI_Test.zip : https://st--c.eu10.content.force.com/sfc/dist/version/download/?oid=00Db0000000YtG6&ids=0680X000006HtP3&d=%2Fa%2F0X0000000aPX%2FeRDPeKysIhZiBt0NEC5SENyi8Z3MFUSOPoH0oREnyYs&asPdf=false

SCHEMATIC1___Edici_n_Full_V1_09_for_ST.pdf : https://st--c.eu10.content.force.com/sfc/dist/version/download/?oid=00Db0000000YtG6&ids=0680X000006HtIl&d=%2Fa%2F0X0000000aLI%2Fn_87K2az3QvH6m557MpqBWsDBx3G4uLoKU6bwXkCC7g&asPdf=false

kleshov · ‎2007-04-13

Posted on April 14, 2007 at 04:23

It could be a hardware problem. In case of poor PCB board layout, switching noise could feed into the WE input of the RAM chip overwriting its contents. Make sure you follow best practices for PCB board layout. Also make sure you have enough decoupling capacitors on the PCB. One capacitor per pair of IC power supply pins is good practice. Resistors on the digital outputs (like address bus outputs) help reduce switching noise. By the way, there is no need to pull unused IO port pins low: at power-up MCU ports have built-in weak pull-ups switched on.

Regards,

- mike

rlobos · ‎2007-04-16

Posted on April 16, 2007 at 11:45

Mike, thanks for your reply,

But our design is EMC compliant and if the PCB design is poor the error it would take place in random form (by noise) or many cells, but that it doesn't happen.

When I read a cell on SRAM only two fixed cells in RAM are overwrited!!! the other cells works fine, and this happens in different Prototype boards (in same cells address)!!!

Regards,

RL

kleshov · ‎2007-04-16

Posted on April 16, 2007 at 12:47

I had a look at the memory test code you used. In a situation like this there are many test you can perform. For example, you could run a test using 16-bit bus accesses. Also you could try different order of addresses and different data patterns. Tests like these could narrow down the search. Once you have a short piece of code reproducing the problem, you can monitor activity on the external bus with a scope to see where it goes wrong.

Regards,

- mike