Posted on May 17, 2011 at 09:36I had difficulties clearing interrupt generated by the PISF (Periodic Interrupt Flag) which should be cleared by reading RTC_SR (RTC Status Register )
http://mcu.st.com/mcu/modules.php?mop=modload&name=Splatt_Forums&file=viewtopic&topic=4983&forum=21 Quote:
PISF: Periodic Interrupt Flag
This bit is set by hardware. It does not set when the RTC is running on battery. It is cleared by reading the register.
0: No periodic event
1: A periodic event occurred as configured by the PISEL bits in the RTC_CR register.
An interrupt is generated if the PIE bit in the RTC_CR register is set.
In fact this is correct, but the interrupt ''VIC1.8 RTC Logic OR of Alarm, Tamper, or Periodic Timer interrupts'' is not cleared by this. As should.
Quote:
IRQStatus[15:0]: IRQ Status bits
These bits are set by hardware after masking by the VICx_INTER and VICx_INTSR
registers. An active bit will remain high until software clears the interrupt in the
registers of the peripheral which sourced the interrupt event. Each bit corresponds
to an input channel. IRQStatus0 gives the status of channel VICx.0 and
IRQStatus15 gives the status of channel VICx.15 (see Table 8.).
My experience (solution) is that the way to clear the PISF interrupt (not PISF itself) is to write 0000 to PISEL[3:0] in RTC_CR during the interrupt, than enable it back. You still have to read RTC_SR to clear the PISF but this is not directly linked to the interrupt signal.
Is this somewhere allready explained ?
regards,
Andras
