Posted on October 28, 2005 at 14:30Greeting,
In section 2.1.7.2 of the STR71x reference manual rev 6, a reference is made to PWD bit of the FLASH_CR0. However, the FLASH_CR0 is not documented.
For future revision of the STR71x reference manual, it could be a good idea to complete the information about FLASH register. Specifically:
FLASHR->CR0
FLASHR->CR1
FLASHR->DR0
FLASHR->DR1
FLASHR->ER
In the meantime, I would like to get more detail about the following item:
1) What is the PWD bit write sequence? Do we have to set a write enable bit before setting the PWD bit? What is the position of the PWD bit in the FLASH_CR0 register?
2) If I am running out of FLASH memory, and I put the FLASH in power down mode using the PWD bit of FLASH_CR0, what is the behaviour? Does the FLASH power down command is applicable immediately or only when system goes to Stop mode? Does the PWD useful only with Stop mode or also useful in Standby, WFI and LPWFI?
I'm looking forward to your feedback.
Regards,
PGagnon
