Timer 0 OCMPA interrupt reset flag.

ongth60 · ‎2005-05-19

Posted on May 19, 2005 at 13:20

ongth60 · ‎2005-04-14

Posted on April 15, 2005 at 00:27

Hi,

Im trying to use Timer 0 as a background timer which interrupts at an interval of 10ms and increase the counter to count to 1s and toggle the LEDs at interval of 1s.

Im using STRFZ7102T6 and RVDK 1.6, running at 16Mhz and setting the APB2 clock to 4 Mhz.

Below is my main.c

#include ''71x_lib.h''

int main(void)

{

#ifdef DEBUG

debug();

#endif

// Configure P0.0 - P0.3 as Output Push-Pull

GPIO_Config(GPIO0, 0x000F, GPIO_OUT_PP);

// Initialise the GPIO0.

GPIO_WordWrite(GPIO0, 0x0000);

//----------------------------------------------------------------------

// Configure the RCCU for APB2(which interfaces Timer0).CK=16MHz(EVAL Board).

//-----------------------------------------------------------------------

RCCU_MCLKConfig(RCCU_DEFAULT);

RCCU_Div2Config(ENABLE); RCCU_RCLKSourceConfig(RCCU_CLOCK2);

RCCU_PCLKConfig(RCCU_RCLK_2);

APB_ClockConfig(APB2,ENABLE,TIM0_Periph);

//-----------------------------------------------------------------------

//Configure the EIC Timer0 IRQ channel

//-----------------------------------------------------------------------

EIC_IRQChannelPriorityConfig(T0OC1_IRQChannel , 10);

EIC_IRQChannelConfig(T0OC1_IRQChannel, ENABLE);

EIC_IRQConfig(ENABLE);

//-----------------------------------------------------------------------

// Configure the Timer 0

//-----------------------------------------------------------------------

TIM_Init(TIM0);

TIM_ClockSourceConfig(TIM0, TIM_INTERNAL);

TIM_PrescalerConfig(TIM0, 0x00);

TIM_OCMPModeConfig(TIM0, TIM_CHANNEL_A, 0x9C40, TIM_TIMING, TIM_LOW);

TIM_ITConfig(TIM0, TIM_OCA_IT, ENABLE);

TIM_CounterConfig(TIM0, TIM_START);

while (1);

}

Below is the my ISR handler :

void T0OC1_IRQHandler(void)

{

static u16 count = 0;

count++;

TIM_FlagClear(TIM0, TIM_OCFA);

TIM0->OCAR = 0x9C40;

if(count = 100)

{

GPIO_WordWrite(GPIO0, (0x000f&~GPIO_WordRead(GPIO0)));

count = 0;

}

My questions are:

1. Do I need to clear the interrupt flag OCMPA in the ISR handler or it is done automatically? Theres nothing mentioned in the TIMER section reference in the STR71 Reference Manual. I've just stumble upon TIM_FlagClear(TIM0, TIM_OCFA) function which clears the flag, thats why im putting it in the handler.

2.Also, what happens when OCAR values is equal to the counter value? Im using OCMPA,which interrupts at every 10ms. So, the timer counter will start counting till it reaches the OCAR value(0x9C40). Then, it generates an interrupt request. What will happen to the counter value? Will it continue to count to 0xffff or will it reset to 0x0000? If it resets to 0x0000, is it done automatically or is it resetted when i reload the value of OCAR?

3. In the STR71 Reference Manual, it states :

The value in the 16-bit OCiR register and the OLVLi bit should be changed after each successful comparison in order to control an output waveform or establish a new elapsed timeout.

So, does that mean that i ONLY need to reload the OCAR value in the interrupt handler if my elapsed time out is different ? In my case, I dont have to reload it rite cos Im interrupting at a constant elapsed time?

4.Lastly, in STR71 manual, it states :

8.3 Special Features

Timer0:

• T0.EXTCLK input is directly connected to CK pin through a prescaler, which divides the

input frequency by eight.

Am I configuring my timer 0 clck to be equal 4Mhz correctly?. Im afraid that this special feature might interfere with my configurations. Btw, what does T0.EXTCLK referring to?

Pls advise.

Rgrds,

TH Ong

ongth60 · ‎2005-04-15

Posted on April 16, 2005 at 04:41

Hi RISC,

Thanks for answering my questions.

I've ran the program. I have the following questions:

1.If clock of timer 0 is connected directly to the CK pin via 1/8 prescaler, does configuring the RCCU for APB2 clock affect the clock of timer 0? Does that mean that timer 0 clock bypass the RCCU block and connect dirrectly to the CK pin via 1/8 prescaler?

2. Also, i found out that TIM_PrescalerConfig(TIM0, 0x2F) prescaler function doesnt prescale the timer 0 clock, instead the timer 0 clock is 1/8 of CK clock. Pls advise.

3.In the program, the RCCU clock is not configured before timer 1 is used. The period measured during HIGH level is 240ms while the period measured during LOW level is also 240ms, meaning that timer 1 OCB interrupts at every 240ms. The configuration of timer 1 is :

TIM_Init(TIM1);

TIM_ClockSourceConfig(TIM1, TIM_INTERNAL);

TIM_PrescalerConfig(TIM1, 0x2F);

TIM_OCMPModeConfig(TIM1, TIM_CHANNEL_B, 0x9C40,TIM_WAVE, TIM_LOW);

TIM_ITConfig(TIM1, TIM_OCB_IT, ENABLE);

TIM_CounterConfig(TIM1, TIM_START);

From my calculation, assumption of timer 1 clock is 16Mhz, where prescaler of timer 1 is 0 due to the function TIM_Init(TIM1). However, i dont know the clock frequency of RCLK.My assumption is that the RCLK clock source is from CLK2. My calculation is based on the assumption that timer 1 clock is 16Mhz is:

16MHz/ Prescaler = 16Mhz/47 + 1 = 16MHz/48 = 333 333.34 Hz = 3 microseconds.

OCBR = 0x9c40 = 40 000d.

So, 3 microseconds * 40000 = 120 miliseconds.

So, calculated value = 120 miliseconds while measured value =240ms. I suspect that the timer 1 clock is 8MHz, which means it is prescaled someway along the way.

Can u enlighten me on the calculation?

4. Without configuring the RCCU clock, what will be the default APB2 clock,APB1 clock, MCLK clock, RCLK and CLK2 settings?

5.I encountered these in the interrupt handler:

TIM1->OCBR += 0x9C40;

My understanding of the above code is

TIM1->OCBR = OCBR + 0x9c40.Why can't I write TIM1->OCBR = 0x9c40?

Can you pls explain the below code:

TIM1->CR1^=1<

My understanding is that ur toggling CR1.9. What does ^ stands for?

Best rgrds,

Ong

ongth60 · ‎2005-04-18

Posted on April 18, 2005 at 23:46

Hi RISC,

Ya, im using STR710FZ2T6 and STR710F Eval kit to develop the platform for my project. I need the support of the forum to understand better as i need to rush to meet dateline and the product is quite new in my place. Anyhow, the support has been fast and resourceful. Cheers guys especially the moderators!.

One final question,

5.If you do not change the OCiR register value, the next interrupt will be generated after 0x63C0+0x9c40 = 0x10000 clock cycle.

:D

This interrupt will call the timer 0 overflow ISR rite if timer 0 overflow interrupt if enabled and not the OCMPA ISR?

Regards,

TH Ong

ongth60 · ‎2005-05-10

Posted on May 10, 2005 at 10:47

Hi,

How can I adjust the period of when the timer needs to overflow in order to generate the corresponding timer overflow interrupt? I know I can do this using OCMPA or OCMPB to generate the corresponding interrupts at a fixed period. My guess, is the period of the timer overflow is adjusted by changing the frequency of the timer clock. Pls advice.

Rgrds,

ongth60

ongth60 · ‎2005-05-10

Posted on May 10, 2005 at 12:22

Hi,

I did that with Timer 1. I set the prescaler value to 0. The timer clock source is set to internal clock source. I expect the APB frequency to be 8Mhz. So timer1 will overflow at every 1.25 e-7s.

Instead, what I've got is it interrupt at every 8ms. Pls advise.

Warm regards,

ongth60

ongth60 · ‎2005-05-10

Posted on May 10, 2005 at 12:29

My source code would be:

int main()

{

...

EIC_IRQChannelPriorityConfig(T1TIMI_IRQChannel , 14);

EIC_IRQChannelConfig(T1TIMI_IRQChannel, ENABLE);

EIC_IRQConfig(ENABLE);

TIM_Init(TIM1);

TIM_PrescalerConfig (TIM1, 0x00);

TIM_ClockSourceConfig(TIM1, TIM_INTERNAL);

TIM_ITConfig(TIM1, TIM_TO_IT, ENABLE);

TIM_CounterConfig(TIM1, TIM_START);

while(1)

{

}

My interrupt routine will be :

void T1TIMI_IRQHandler(void)

{

TIM_FlagClear(TIM1, TIM_TOF);

GPIO_WordWrite(GPIO0, ~GPIO_WordRead(GPIO0));

}

I've measured the interval between the toggling. Its 8ms.

Pls advise.

Regards,

ongth60

ongth60 · ‎2005-05-17

Posted on May 17, 2005 at 11:39

Hi,

How could I generate an interrupt frequency of 4Mhz then?

Rgrds,

ongth60

ongth60 · ‎2005-05-18

Posted on May 18, 2005 at 23:08

CPU clock is 16Mhz and APB clock is 8MHz. Im using the standard frequency configuration.

Rgrds,

TH Ong