Posted on October 23, 2007 at 08:51This thread is reserved for STMicroelectronics, PLEASE DO NOT REPLY.
Dear,
New revision of
http://STR73x Reference manual
http://www.st.com/stonline/products/literature/rm/13682.pdf
Rev2 is available for download from the web site;
http://www.st.com/mcu/familiesdocs-86.html
Here below, changes compared to the last revision
Rev1;
+ Updated
Section 14.3.10:''Pulse width modulation mode''- Added period formula when OCBR> OCAR
- Updated period formula when OCBR and OCAR are loaded with FFFCh.
+ Modified
Section 6.1.2:''Alternate function I/O (AF)''- For alternate function inputs, the port must be configured in Input
mode and the input pin must be driven externally.
+ Added
Section 11.3.3:''RTC flag assertion''- Added Note: If RTC interrupts are used during Run, Slow, WFI or LPWFI
modes the RTC clock must be at least 4 times slower than MCLK clock.
+ Modified
Section 11.4.3:''RTC Prescaler Load Register High (RTC_PRLH)''- Bits 3:0 =
PRL[19:16]: These bits are used to define the counter clock frequency according to the following formula:
fTR_CLK = fRTC/64/2 ; if PRL[19:0] =0
fTR_CLK = fRTC/64/(PRL[19:0]+1) ; if PRL[19:0] > 0
+ Updated
Section 11.4.4:''RTC Prescaler Load Register Low (RTC_PRLL)''- Bits 15:0 =
PRL[15:0]: These bits are used to define the counter clock frequency according to the following formula:
fTR_CLK = fRTC/64/2 ; if PRL[19:0] =0
fTR_CLK = fRTC/64/(PRL[19:0]+1) ; if PRL[19:0] > 0
- Added note: The reset value sets the TR_CLK signal period to 1 sec
for an input clock of 32 kHz.
+ Updated
Section 18.2.5:''Start-up status''- The MSTR bit must be set high and then the BSPI must be enabled.
+ Updated
Section 19.4.6:''UART control register (UARTn_SR)''- RxBufFull changed to RxBufNotEmpty.
+ Updated
Section 17.4:''Interrupts''- SCLFAL signal removed from
figure 62:''Event flags and interrupt generation''+ Added
Section 22.1.1:''JTAG ID code''Best Regards ;)
