2003-07-25 02:32 AM
2003-07-25 02:16 AM
The SPIF bit seems not to be reseted after a write to the SPIDR ?
My address is sent first OK, but the following data seems not to be sent ... why ??? bset SS_SPI ;SS/ = 1 sélection RTC ld A,#7Ch ;SPI enabled and interrupt disabled - Serial Clock at Fcpu/4 ld SPICR,A ;SCK is at high level in idle state and ;The second clock transition is the first capture edge ld A,#03h ;SPI output enabled - SS/ external pin = CE RTC ld SPICSR,A ;SSI = 0 => Slave selected ld A,SPICSR ;Reset bit SPIF ld A,#8FH ;Sélection adresse contrôle register ld SPIDR,A att_spi0 btjf SPICSR,#7,att_spi0 ;Wait until end of transmission ld A,SPICSR ;Reset bit SPIF ld A,#00H ;Initialisation du registre de contrôle à 0 ld SPIDR,A2003-07-25 02:32 AM
To clear the SPIF you have to read or write the SPIDR not the SPICSR after an access to the SPICSR. I read the SPIDR as it covers both slave and master mode.
Taken from datasheet: Clearing the SPIF bit is performed by the following software sequence: 1. An access to the SPICSR register while the SPIF bit is set 2. A read to the SPIDR register. Hope this helps SJO