Posted on May 17, 2011 at 11:51Hey all,
I wonder if anyone knows the reason for this: I'm starting my first project with a uPSD3454EB40T6 (previously used uPSD32XX), and so I thought I'd switch from PSDSoft to the new CAPS tool for setting up the PSD module.
When choosing message map templates, I notice that for a few of them, there's the following note:
''Note : For devices running at 24 MHz or higher, this memory map requires 1 additional wait state for SRAM accesses (read and write). This extra wait state must be added to the specified clock period values for the RDW and WRW fields in the BUSCON special function register as shown in the data sheet.''
This seems to be related to trying to max-out the code space and still provide IAP. I THINK it has to do with the CSIOP registers being overlayed on top of the SRAM instead of the flash, but I'm not certain. Could anyone elaborate what constraints on the memory map exist to cause us to have to modify the SRAM wait states?
-Phaze426
