2009-11-11 03:41 PM
2011-05-17 02:52 AM
Hi,
I am using upsd3234. I want to interface 32K SRAM M48T35Y to upsd3234. My interface is like this: PA0 - PA7 of upsd3234 to D0 - D7 of M48T35Y. AD0 - AD7 of upsd3234 to A0 - A7 of M48T35Y. A8 - A11 of upsd3234 to A8 - A11 of M48T35Y. /RD, /WR to directly connect to M48T35Y. My question is how memory mapping and paging is structured ? Thank you.