Posted on May 17, 2011 at 09:59Hello,
I have a question concerning the flash configuration. In the most examples from ST, the FMI clock is set to 96 MHz and the Flash is configured with the following settings.
FMI_Config(FMI_READ_WAIT_STATE_2, FMI_WRITE_WAIT_STATE_0, FMI_PWD_ENABLE, FMI_LVD_ENABLE, FMI_FREQ_HIGH);
According to the STR912FA manual, the FMI clock can be set to 96 MHz if the flash size is <= 512 KB. But what is the right number of read wait states?
In the datasheet of the STR912FA is written on page 69 the follwing note :
Note: Flash read access for sequential addresses is 0 wait states at 96 MHz. Flash read access
for non-sequential accesses requires 2 wait states when FMI clock is above 66 MHz. See
STR91xF Flash Programming Manual for more information.
In the STR91xFA Flash programming manual on page 32 for Flash configuration you can find the following note :
Note: Wait States are inserted only for non-bursting Flash read bus cycles. One
wait state is required for a FMI bus clock frequency of 66 MHz or less. Two wait
states are required for 75 MHz bus clock frequency.
What is now the correct setting? Two wait states (according to the datasheet) or 3 wait states (according Flash manual)?
King regards
Alex
