2007-08-13 07:43 PM
2007-08-10 10:59 AM
Hi all
Does anyone know whether or not when using flash burst mode there are any ''page'' boundaries that incur that 1 cycle wait state for non sequential accesses? I'm interested to know whether or not I can read a long table out of flash with consistent timing. Thanks in Advance :o em2007-08-10 08:47 PM
I don't know the answer to the question, but I have some ideas. First, you could test flash read time using a working MCU board and a scope. Second, if you need consistent read times, you can read the table in a non-sequential manner (say, in reverse order) to guarantee 1 wait state for each read.
2007-08-13 06:27 AM
Thats an interesting approach Volius. However if there is a page access time hit wouldn't you still incur it regardless of which direction you are going?
em2007-08-13 07:43 PM
Here is what the datasheet says:
High Speed Flash Memory (STR71xF)
The Flash program memory is organized in two banks of 32-bit wide Burst Flash
memories enabling true read-while-write (RWW) operation. Device Bank 0 is
up to 256 Kbytes in size, typically for the application program code.
Bank 1 is 16K bytes, typically used for storing data constants.
Both banks are accessed by the CPU with zero wait states @ 33 MHz
...
Flash memory can be accessed in two modes:
- Burst mode: 64-bit wide memory access at up to 50 MHz.
- Direct 32-bit wide memory access for deterministic operation at up to 33 MHz.There is no mention of pages in the datasheet. It is consistent with my understanding that NOR flash memories don't have pages, while NAND flash memories do. 64-bit burst mode access probably means that flash memory is read 64 bits at a time, caching some data for future reads. According to the datasheet, there is a way to guarantee consistent flash read times: you should switch off burst mode and lower CPU frequency down to 33 MHz.