clock switching

jgoril · ‎2006-09-18

Posted on September 18, 2006 at 13:25

clock switching

jgoril · ‎2006-09-18

Posted on September 18, 2006 at 09:20

Hi. I use 10 MHz clock signal at CK pin in my application (using STR711FR2). Internally I want to set-up MCLK to 40 MHz and PCLK2 to 5 MHz. I have observed that I must insert some nop cycles after clock switching in order to run my application correctly. But why? Is there any clock stabilisation time? How long is it? Where can I find related data? Thanks a lot.

kleshov · ‎2006-09-18

Posted on September 18, 2006 at 13:25

After adjusting the PLL, you have to wait until it's stabilized before you can use PLL output for system clock. It's described in the reference manual, section 3.4.1 - PLL1 Clock Multipier.

PLL lock time is specified where you would expect: in the datasheet, section 2.3.3 - Clock And Timing Characteristics. Make sure you have the latest version of the datasheet, dated August 2006.

Regards,

- mike