Posted on September 29, 2005 at 18:53We're using the STR710 to read data from an external ADC.
The ADC acts as an SPI master and sends a 96 bit burst of data with an SPI clock of 500kHz. The data represents 6 16 bit values., and the burst frequency is 2 kHz (1 6-word burst every 0.5ms) The transmission is one way, the ADC doesn't have a MISO pin.
The ADC is wired so that its MOSI pin is connected to BSPI0 MOSI pin, and its SCK_OUT pin is connected to the BSPI0 SCLK pin. BSPI0 SS pin is tied to ground and BSPI0 MISO pin is open.
The STR7 uses a 16 MHz oscillator and the system clock is 48 MHz. APB1 and APB2 clocks are 24 MHz.
The BSPI0 is enabled in the BOOT_CR register.
BSPI0_CSR1 is 0101 0100 1001 1101.
(6 word receive FIFO, 16 bit word, data sampled on first clock edge, clock active high, bus error int. enabled, receive error int. enabled, interrupt on FIFO full, slave mode, BSPI system enabled.)
BSPI0_CSR2 is 0000 00xx xxxx xxx0.
(No transmit interrupt, 1 word transmit FIFO, FIFO not reset.)
BSPI0_CLK is 0000 0000 0000 1000.
(APB1 divider set to 8.)
When the FIFO is full, we receive an interrupt. We check to see the source of the interrupt. If it is only the FIFO full (no overflow, no bus error) we read the BSPI0_RXR 6 times and put the data in an array. If we read the RXR in a tight loop (no delay) all 6 words read as the same value. This can be any 1 of the 6 correct values from the ADC. If we insert a delay of at least 8 clocks between reads, the 6 words are the correct values from the ADC. We never get bus error or overflow interrupts so the FIFO is emptied in both cases, but the data is lost unless a delay is inserted between reads of RXR.
Is there some reason we must wait between reads of BSPI0_RXR to get the correct data? The Rx FIFO for the UARTs doesn't need this wait to work properly.
This is a problem for us since adding the delay adds 40 clocks to each interrupt, and since we don't understand why it is happening.
