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Debugging Dual Core SPC56

Matthew Richardson
Associate II

‎2018-02-23 01:14 AM

Posted on February 23, 2018 at 10:14

I have a DPM configuration for SPC56EL70.  I initially had some trouble getting the debugger to connect to the target ( could connect fine in LSM.)  The problem had to do with not clearing the LSM_DPMB bit.  Erwan found this FAQ which left me some really good bread crumbs:  

https://www.pls-mc.com/microcontroller-faqs/faqs-a-1291.html?sh8=bHNt

 

Using PLS-UDE v4.8:

1) Connect to the target using a known working LSM mode configuration.

2) Open the FLASH/OTP Memory Programming Tool

3) Select 'SHADOW FLASH' from Memory Device dropdown and check 'Enable' to make the connection, then Exit.

4) Open a Memory Window and navigate to BIU4 address, which is 0x00FF_FE10

5) Change the Address value to FFBF_FFFF, and the field will be red indicating that it doesn't match.

6) Open the FLASH/OTP Memory Programming Tool again and notice that the Program All button is enabled, then program and verify.

7) Power off the processor and restart.  Reconnect using a DPM configuration/workspace and you should be able to connect to the target.  There should be both Core0 and Core1 binaries/symbols when Load Program is selected from the File Menu.

I followed those steps with some success of being able to connect and dataload.  I don't know if what I did is correct (even if it does connect) as I read the reference manual, bit 0x0040_0000 is not the LSM_DPMB bit as described in User Options Table.  Bit 9, not bit 22 should toggle

LSM_DPMB.

 Maybe the BIU4 address doesn't map the same as the User Option Bits?  I don't know.  It seems esoteric.

The problem:

The problem I am having is that when I debug, the program gets stuck in SPCSetRunMode() waiting for ME.IS.R != 0U.  If I disconnect from the target and reset, then the program runs while not debugging.  However, my main_core1()  routine is never started.  My guess is that I'm either not configured correctly to debug, or that there is a PLS - .wsx alignment issue.  Does anyone have a wsx and a small DPM helloworld out there?

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zambrano.luigi
Senior III
In response to Matthew Richardson

‎2018-03-02 04:09 AM

Posted on March 02, 2018 at 12:09

Hi Matthew,

in attachment you can find a modified version of the SPC5Studio DualCore test application for Leopard Discovery in which the interrupts of the PIT0 (used as system timer) are managed by the Core1 while the interrupts of the SERIAL are managed by the Core0. You can import it in your SPC5Studio, check the modifications (summarized in the patch file), compile and execute it on your platform. In any case, in order to manage the interrupts of PIT0 on Core1, the following modifications are required:

1. Define in the file int.c the macro's for the initialization of the interrupts of the Core1.

2. Set in the file systimer.c the priority of the PIT0 interrupt to 0 for the Core0 (PIT0 interrupts disabled on Core0) and toSPC5_SYSTIMER_IRQ_PRIORITY for the Core1.

3. Duplicate in irq.c the same initializations made for Core0 also for the Core1.

4. Define in the file ivor.s the_C1_IVOR4 handler and the function_spr_init1 (invoked in themain_core1 function)

I'm available for any other clarification.

Best regards,

Luigi

________________

Attachments :

SPC56ELxx_RLA DualCore Test Application for DiscoveryPlus.zip : https://st--c.eu10.content.force.com/sfc/dist/version/download/?oid=00Db0000000YtG6&ids=0680X000006HxvL&d=%2Fa%2F0X0000000b2J%2Fl7GbWgFIsRD6MN9oFtPZxnJwkurwCJUkK_Y5wS7QzEM&asPdf=false
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