2022-08-06 03:09 AM
Hi,
i have spc560p50l5 if i enable irqIsrEnable(); in debug it crash. (no codes execuded after).
If i comment //irqIsrEnable(); debug works, but osal not starts.
In assembly code of swirq_enable there are a lot OF_SE_ILLEGAL
0x400001E8 00 00 SE_ILLEGAL
0x400001EA 00 00 SE_ILLEGAL
/**
* @brief Enable software IRQ.
*
* @param[in] irq software irq number
* @param[in] prio interrupt priority
* @param[in] core core to dispatch interrupt
*
* @sa
* INTC_PSR_CORE0, INTC_PSR_CORE1, INTC_PSR_CORE2,
* swirq_disable
*
* @notapi
*/
void swirq_enable(uint8_t irq, uint8_t prio, uint32_t core) {
irq &= 0x1FU;
INTC_PSR((irq)) = INTC_PSR_ENABLE(core, prio);
0x00000014 78 00 01 5C E_B _boot_address (0x00000170)
_disablewatchdog:
0x00000018 70 9F E7 F3 E_LIS R4,0xFFF3
0x0000001C 70 90 C0 00 E_OR2I R4,0x8000
0x00000020 70 78 05 20 E_LI R3,0xC520
}
0x00000024 54 64 00 10 E_STW R3,0x10(R4)
0x00000028 70 7B 01 28 E_LI R3,0xD928
0x0000002C 54 64 00 10 E_STW R3,0x10(R4)
0x00000030 70 7F E7 00 E_LIS R3,0xFF00
}
0x00000034 70 60 C0 0A E_OR2I R3,0xA
0x00000038 54 64 00 00 E_STW R3,0x0(R4)
0x0000003C 00 04 SE_BLR
0x0000003E 44 00 SE_OR R0,R0
_coreinit:
0x00000040 7C 00 02 78 XOR R0,R0,R0
0x00000044 7C 21 0A 78 XOR R1,R1,R1
0x00000048 7C 42 12 78 XOR R2,R2,R2
0x0000004C 7C 63 1A 78 XOR R3,R3,R3
0x00000050 7C 84 22 78 XOR R4,R4,R4
0x00000054 7C A5 2A 78 XOR R5,R5,R5
0x00000058 7C C6 32 78 XOR R6,R6,R6
0x0000005C 7C E7 3A 78 XOR R7,R7,R7
0x00000060 7D 08 42 78 XOR R8,R8,R8
0x00000064 7D 29 4A 78 XOR R9,R9,R9
0x00000068 7D 4A 52 78 XOR R10,R10,R10
0x0000006C 7D 6B 5A 78 XOR R11,R11,R11
0x00000070 7D 8C 62 78 XOR R12,R12,R12
0x00000074 7D AD 6A 78 XOR R13,R13,R13
0x00000078 7D CE 72 78 XOR R14,R14,R14
0x0000007C 7D EF 7A 78 XOR R15,R15,R15
0x00000080 7E 10 82 78 XOR R16,R16,R16
0x00000084 7E 31 8A 78 XOR R17,R17,R17
0x00000088 7E 52 92 78 XOR R18,R18,R18
0x0000008C 7E 73 9A 78 XOR R19,R19,R19
0x00000090 7E 94 A2 78 XOR R20,R20,R20
0x00000094 7E B5 AA 78 XOR R21,R21,R21
0x00000098 7E D6 B2 78 XOR R22,R22,R22
0x0000009C 7E F7 BA 78 XOR R23,R23,R23
0x000000A0 7F 18 C2 78 XOR R24,R24,R24
0x000000A4 7F 39 CA 78 XOR R25,R25,R25
0x000000A8 7F 5A D2 78 XOR R26,R26,R26
0x000000AC 7F 7B DA 78 XOR R27,R27,R27
0x000000B0 7F 9C E2 78 XOR R28,R28,R28
0x000000B4 7F BD EA 78 XOR R29,R29,R29
0x000000B8 7F DE F2 78 XOR R30,R30,R30
0x000000BC 7F FF FA 78 XOR R31,R31,R31
0x000000C0 70 88 E0 00 E_LIS R4,0x4000
0x000000C4 70 80 C0 00 E_OR2I R4,0x0
0x000000C8 70 A8 E0 00 E_LIS R5,0x4000
0x000000CC 70 B4 C0 00 E_OR2I R5,0xA000
.cleareccloop:
0x000000D0 7C 04 28 40 CMPL 0x0,0x0,R4,R5
0x000000D4 E0 06 SE_BGE .cleareccend (0x000000E0)
0x000000D6 1A 04 09 00 E_STMW R16,0x0(R4)
0x000000DA 18 84 80 40 E_ADDI R4,R4,0x40
0x000000DE E8 F9 SE_B .cleareccloop (0x000000D0)
.cleareccend:
0x000000E0 70 60 02 01 E_LI R3,0x201
0x000000E4 7C 75 FB A6 MTSPR 0x3F5,R3
0x000000E8 00 04 SE_BLR
0x000000EA 44 00 SE_OR R0,R0
_ivinit:
0x000000EC 70 60 E0 06 E_LIS R3,0x6
0x000000F0 70 62 C0 00 E_OR2I R3,0x1000
0x000000F4 7C 60 01 24 MTMSR R3
0x000000F8 70 60 E0 00 E_LIS R3,0x0
0x000000FC 70 62 C0 00 E_OR2I R3,0x1000
0x00000100 7C 7F 0B A6 MTSPR 0x3F,R3
0x00000104 00 04 SE_BLR
0x00000106 00 00 SE_ILLEGAL
0x00000108 00 00 SE_ILLEGAL
0x0000010A 00 00 SE_ILLEGAL
0x0000010C 00 00 SE_ILLEGAL
0x0000010E 00 00 SE_ILLEGAL
.unhandled_exception:
0x00000110 78 00 00 00 E_B .unhandled_exception (0x00000110)
0x00000114 00 00 SE_ILLEGAL
0x00000116 00 00 SE_ILLEGAL
0x00000118 00 00 SE_ILLEGAL
0x0000011A 00 00 SE_ILLEGAL
0x0000011C 00 00 SE_ILLEGAL
0x0000011E 00 00 SE_ILLEGAL
_IVOR4:
0x0000012
ALSO I have
Sa 06.08.2022 14:30:46.393, Warning, Core, PpcJtagTargIntf, Unknown break cause !!!
Sa 06.08.2022 14:30:46.406, Warning, Core, CallFrame, could not read memory at 0x0000000084D9F412
Sa 06.08.2022 14:30:47.379, Warning, Core, PpcJtagTargIntf, Unknown break cause !!!
Sa 06.08.2022 14:30:47.391, Warning, Core, CallFrame, could not read memory at 0x0000000084D9F412
How can i solve this?
Thank you in advantages
Solved! Go to Solution.
2022-08-10 12:55 AM
I solve change board
2022-08-06 08:34 AM
Check whatever you're enabling is actually handled properly.
Perhaps stack,vector tables, ISRs, etc.
Start with simple working examples,
Review all available technical documentation for the core.
2022-08-10 12:55 AM
I solve change board