Slow reading of AIS328DQ output

[Central SUPPORT]

My question concerns the ZYXDA status bit of STATUS_REG (27h)

If I'm reading data out at a significantly lower rate (e.g. 25Hz) than the device is internally generating data (100Hz) is there any need to monitor this status bit?

Asked another way, Can I asynchronously read back from the device as long as I'm doing so slower than the device is converting? Or alternatively, is the last conversion buffered?

- I'm not at all concerned about data over-runs.

The data sheet implies there may be a loss of precision if you don't stay synchronized with the conversion process. I just don't have the resources to poll that data available bit continuously.

NOTE: This question and answer originated from a customer support case which was handled by us. We regularly review support cases and add any helpful ones here for all to benefit from.

[Central SUPPORT · Accepted solution]

No problem to read slower than the ODR rate. Data will be overwritten by new set of data. You may just lower the ODR rate (to reduce noise and power consumption) if you really don't need data so fast. 

I suggest to enable the BDU bit of CTRL_REG4 (23h) to inhibit continuous updating of lower and higher register parts and prevents reading data from different sample cycles (see datasheet paragraph 7.5, page 30 for more info)