Not receiving FIFO threshold interrupt in LSM6DSL

[pshin.1]

Hello,

In my application, I need LSM6DSL to generate an interrupt when configured FIFO threshold is reached. I am using FIFO for accelerometer and gyroscope.

My configuration is as below,

FIFO_CTRL5 = 0x09 // ODR 12.5 Hz, FIFO mode

CTRL3_C = 0x 44 //BDU, Reg addr increment

FIFO_CTRL1 = 0x3C //Fifo threshold

INT1_CTRL = 0x08 //Route fth signal on INT1 pin

CTRL1_C = 0x48 //Select LPF BW, Set ODR and FS

FIFO_CTRL3 = 0x09 //Set FIFO ODR for gyroscope and accelerometer

CTRL2_C = 0x18 //Set gyroscope ODR and FS

After this configuration I can see that Watermark flag getting high when the configured threshold level for FIFO is reached. But I am not able to get the interrupt on INT1 pin for the same event.

Please help me if I am missing anything.

Thanks in advance.

[Eleon BORLINI]

Hi @pshin.1​ ,

the configuration seems to be OK, and you are routing fth signal on INT1 pin (INT1_CTRL = 0x08).

May I ask you to check the following cases:

• Configure the routing of the interrupt at the end of the configuration flow --> INT1_CTRL = 0x08 //Route fth signal on INT1 pin after the other commands
• Set the STOP_ON_FTH bit in FIFO_CTRL4 (09h): if it is set to '1', FIFO depth is limited up to FTH [10:0] bits in FIFO_CTRL1 (06h) and FIFO_CTRL2 (07h).
• INT1 detection is failing --> you can see if something changes by latching the interrupt enabling the LIR bit in TAP_CFG (58h) register (datasheet p.87)
• INT1 is not physically working --> can you try with another interrupt (different from the FIFO one?)

-Eleon

[pshin.1]

Hi Eleon,

I tried out your suggestions and the outcome is as below,

• Configure the routing of the interrupt at the end of the configuration flow --> INT1_CTRL = 0x08 //Route fth signal on INT1 pin after the other commands

-No interrupt received.

• Set the STOP_ON_FTH bit in FIFO_CTRL4 (09h): if it is set to '1', FIFO depth is limited up to FTH [10:0] bits in FIFO_CTRL1 (06h) and FIFO_CTRL2 (07h).

-No interrupt received. When I enabled STOP_ON_FTH bit, no. of data samples in fifo status reg were always 0.

• INT1 detection is failing --> you can see if something changes by latching the interrupt enabling the LIR bit in TAP_CFG (58h) register (datasheet p.87)

-No interrupt received.

• INT1 is not physically working --> can you try with another interrupt (different from the FIFO one?)

-No interrupt received. I enabled DRDY on INT1 pin for gyroscope and accelerometer(INT1_CTRL = 0x03) but no success.

The only problem I can think of is, INT1 pin is not connected to host processor which is unlikely.

[Eleon BORLINI]

Hi @pshin.1​ ,

it makes sense that you cannot detect the interrupt if STOP_ON_FTH is enabled, it was just for checking.

Just for my clarification, does CTRL1_C register refer to CTRL1_XL (10h) one and CTRL2_C register refer to CTRL2_G (11h) one, right?

From you test we cannot exclude issues on the INT1 physical connection (from the device to the application processor), or internal to the sensor (I believe this is a little more difficult because open-short and leakage tests are mandatory in the inline production testing).

Another test you can perform is to route the interrupt on the INT2 pin, if it is connected to the application processor too:

INT1_CTRL = 0x00
INT2_CTRL (0Eh)  = 0x80 //Route fth signal on INT2 pin

Another test you could run is to initialize the device in Continuous mode and then to switch in FIFO mode, configuring the IMU in the same way.

-Eleon

[pshin.1]

Hi @Eleon BORLINI​ ,

Yes. CTRL1_C refers to CTRL1_XL and CTRL2_C refers to CTRL2_G .

INT1 pin is physically connected to host processor(Checked for continuity).

I cannot route the signal on INT2 pin as of now since it requires some hardware modifications.

Whenever I do this exercise, I have to configure INT2 = 0x08 (not 0x80) right?

I tried switching from continuous mode to FIFO mode but did not get the interrupt.

However, I captured the graph on INT1 pin and below are the observations.

1.INT1 pin remains low immediately after the board is powered ON.

2.INT1 pin goes to logic high state after 1878 ms after the board is powered ON.

3.The observations in 1 and 2 mentioned above can be witnessed even if FIFO is set in bypass mode.

4.The observations in 1 and 2 mentioned above were not witnessed if no register of gyroaccelerometer was configured.

EDIT,

After configuring DRDY_PULSE_CFG_G = 0x80, I can see the interrupts on INT1 but these are DRDY interrupts even if I haven't configured DRY on INT1. How can I get FTH interrupt only?

Thanks,

Pranav

[Eleon BORLINI]

Hi @pshin.1​ ,

>> 2. INT1 pin goes to logic high state after 1878 ms after the board is powered ON.

Is this issue related to this other post from you, or it is another problem?

-Eleon

[pshin.1 · Accepted solution]

Hi Eleon,

Yes, Issue 2 is related to the other post from me.

I am also able to suppress DRDY interrupts after deliberately setting the corresponding bit to zero.

We can close this thread and can discuss the specific issue on the other thread.

Regards,

Pranav