LSM6DSRX ODR variability @ 1666, 3332 and 6667 Hz?

Singh.Harjit · ‎2021-04-15

I would like to determine if this is stable enough to be the timebase for a servo loop and/or doing integration when dead reckoning.

Would be great to get this this across PVT (process, voltage, temperature).

Thank you in advance for your help!

Eleon BORLINI · ‎2021-04-16

Hi @Singh.Harjit ,

the answer to your question could be "yes", but we should first define what you do intend for stability of the ODR...

The actual value of the ODR can vary a little with respect to the nominal one (in the range on +-5%), but the variation around that value is very little.

This means that the jitter is very low, in the range of 40ns at 6.6kHz, and lower at 1.6kHz.

Here below some bench data for completeness:

These parameter varies very little versus T and versus Vdd.

My suggestion is to first characterize the actual ODR of your device (for example exploiting the Data-Ready interrupt, or measuring the data output with a scope), and then use this vale as time-base for integration algorithms for your dead reckoning application.

If my reply answered your question, please click on Select as Best at the bottom of this post. This will help other users with the same issue to find the answer faster.

-Eleon

View solution in original post

Eleon BORLINI · ‎2021-04-16

Hi @Singh.Harjit ,

the answer to your question could be "yes", but we should first define what you do intend for stability of the ODR...

The actual value of the ODR can vary a little with respect to the nominal one (in the range on +-5%), but the variation around that value is very little.

This means that the jitter is very low, in the range of 40ns at 6.6kHz, and lower at 1.6kHz.

Here below some bench data for completeness:

These parameter varies very little versus T and versus Vdd.

My suggestion is to first characterize the actual ODR of your device (for example exploiting the Data-Ready interrupt, or measuring the data output with a scope), and then use this vale as time-base for integration algorithms for your dead reckoning application.

If my reply answered your question, please click on Select as Best at the bottom of this post. This will help other users with the same issue to find the answer faster.

-Eleon

Singh.Harjit · ‎2021-04-17

@Eleon BORLINI Thank you! This is exactly the information I was looking for.

Just to close the loop (all puns intended), I will use the data ready interrupt to run the loop. Actually, I'm going to use the data ready interrupt to kick off a DMA read of the IMU and the DMA completion to run the control loop. This won't be the lowest jitter approach but is good enough.

I find it interesting that the jitter is ~40ns. I'm inferring from that the internal clock is 25MHz. The standard deviation is nice and tight (229 parts per million) which tells me that the stability is really good. Congratulations and well done to the ST team!

Understood about the +/-5% range. As you suggested, I'll measure it and adjust the time-base.

All the best.

Eleon BORLINI · ‎2021-04-19

Thank you @Singh.Harjit !

-Eleon