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LSM6DSO Int2 on Int1although it is disabled

CWies.1
Associate III

Hi,

we are using the LSM6DSO in Fifo mode and with the double tap feature. Our firmware configures the Sensor Frontend to give an interrupt at fifo_th on INT1 and for double_tap on INT2. Therefore, we explicitly disabled the INT2_on_INT1 bit inside the CTRL4_C register.

But still we see the the INT2 interrupts on the INT1 line. (See plot)

SCR01.PNG

We always reset the sensor to default. So I guess it seems something is not correctly configured.

Here is the code for configuring the sensor:

 

	// configure for the first time
	ret_code_t err;

	// Get ID
	err = lsm6dso_device_id_get(whoamI);
	if (whoamI[0] != LSM6DSO_ID){
		APP_ERROR_CHECK(NRF_ERROR_NOT_SUPPORTED);
	}

	// Do reset
	uint8_t res;
	err = lsm6dso_reset_set(PROPERTY_ENABLE);
	do {
		lsm6dso_reset_get(&res);
	} while (res);

	// Disable INT2_on_INT1 to avoid wrong Interrupts
	lsm6dso_ctrl4_c_t  ctrl4_c = {0};
	ctrl4_c.i2c_disable = PROPERTY_ENABLE;
	ctrl4_c.int2_on_int1 = PROPERTY_DISABLE;
	writeReg(LSM6DSO_CTRL4_C, (uint8_t *)&ctrl4_c);

	// Disable I3C
	NRF_LOG_INFO("Disable I3C");
	lsm6dso_i3c_disable_set(LSM6DSO_I3C_DISABLE);
	nrf_delay_ms(10);

	// Set BDU
	NRF_LOG_INFO("Set BDU update");
	lsm6dso_block_data_update_set(PROPERTY_ENABLE);
	nrf_delay_ms(10);

	// Set power modes
	lsm6dso_gy_power_mode_set(LSM6DSO_GY_HIGH_PERFORMANCE);
	lsm6dso_xl_power_mode_set(LSM6DSO_HIGH_PERFORMANCE_MD);
	// Set FIFO WATERMARK
	NRF_LOG_INFO("Set FIFO Watermark!");
	err = lsm6dso_fifo_watermark_set(WATERMARK_LEVEL);
	APP_ERROR_CHECK(err);
	nrf_delay_ms(10);
	NRF_LOG_INFO("Set FiFo Batch");
	lsm6dso_fifo_batch_set(LSM6DSO_GY_BATCHED_AT_1667Hz, LSM6DSO_XL_BATCHED_AT_1667Hz);
	nrf_delay_ms(10);

	// Set fifo mode
	NRF_LOG_INFO("Set FiFo Mode");
	lsm6dso_fifo_mode_set(LSM6DSO_STREAM_MODE);
	lsm6dso_pin_int1_route_t pin1;
	pin1.double_tap = PROPERTY_DISABLE;
	pin1.single_tap = PROPERTY_DISABLE;
	pin1.fifo_th = PROPERTY_ENABLE;
	lsm6dso_pin_int1_route_set(pin1);
	NRF_LOG_INFO("Setting Interrupt Config");
	nrf_delay_ms(10);

	NRF_LOG_INFO("Set ODR");
	lsm6dso_xl_data_rate_set(LSM6DSO_XL_ODR_1667Hz, LSM6DSO_16g);
	nrf_delay_ms(10);
	lsm6dso_gy_data_rate_set(LSM6DSO_GY_ODR_1667Hz, LSM6DSO_2000dps);
	nrf_delay_ms(10);

	// set double tap
	lsm6dso_double_tap_set();
	lsm6dso_pin_int2_route_t pin2 = {0};
	pin2.double_tap = PROPERTY_ENABLE;
	pin2.single_tap = PROPERTY_DISABLE;
	lsm6dso_pin_int2_route_set(pin2);
	NRF_LOG_INFO("Config completed");

 

Any help or comment would be apreciated.

1 ACCEPTED SOLUTION

Accepted Solutions
CWies.1
Associate III

Found a solution it was the SPI code not the sensor.

View solution in original post

4 REPLIES 4
CWies.1
Associate III

Furthermore, if this happens somehow the interrupt pin of the LSM6DSO goes permanently HIGH. Any suggestion?

Federica Bossi
ST Employee

Hi @CWies.1 ,

Have you already check your code with our examples that you can find on github? Maybe you can find an error in your code, otherwise, if you have still the problem, we can check together.

Let me know.

In order to give better visibility on the answered topics, please click on 'Accept as Solution' on the reply which solved your issue or answered your question.

Hi Federica,

the problem still persists. I have double-checked the example code but still, it is not reasonable for me why the interrupt for double tap on INT2 happens as well on INT1 although it was explicitly switched off. Do you have an example with both interrupts enabled?

kind regards, C.W.

CWies.1
Associate III

Found a solution it was the SPI code not the sensor.