LIS2DW12 shared SDI and CLK lines cause current leaks

[APipm.1]

Hello!

We have developed two types of custom boards, with two different MCUs.

On board number 1, each peripheral unit has its own SPI lines dedicated to it. On board number 2, the number of GPIOs has decreased, so we decided that the CLK and MOSI (SDI) legs will be shared among peripherals, and the MCU will select the unit it talks to via different CS lines.

This should not be a problem, since pull ups are only present on the CS and SDO lines.

In practice, we see around a 5uA current draw when all peripherals are turned off, which leads us to suspect some peripheral is no setting its GPIOs to float when its is being turned off.

We tried removing each peripheral from our boards separately, and surprisingly, when removing the ST lis2dw12 from the board, the current leak stops. removing all other peripherals does not reduce power draw.

Notice- we only see this on the board where the MOSI and CLK lines are shared, not on the board where each SPI pin is separated. This is probably because in both boards, the MCU GPIOS are set to 'float', i.e high Z, disconnected when the device enters its lowest power mode, which is where we see this ~5uA leak.

So, we have the same piece of code (aside from different GPIO mapping) running on two devices, where if two SPI lines which should not be pulled are shared between devices, the Lis2dw12 leaks ~5uA of current.

Has anyone seen anything like this?

A bit of info- We're working at VDD=3V. VDD and VDDIO lines are connected to each other. The board follows the LIS2DW12 electrical connections diagram from page 19 of the Datasheet.

Thanks!

[Eleon BORLINI]

Hi @APipm.1​ ,

ya, 5uA should be the current consumption in LP with ODR 100 Hz, and not in Power down...

I have some question to try to narrow down and better understand this issue:

Are you experiencing this over-consumption on all your "type 2" boards, right? And are you measuring this leakage before setting the device, so that it is in power down mode?

>> the MCU GPIOS are set to 'float', i.e high Z, disconnected when the device enters its lowest power mode

What if you set high the SDO/SA0 and CS pins instead of leaving it high Z (if these lines are not shared)? I'm wondering if there could be any parasitic or high resistance path to GND that make these pins conducting... could you please check this point?

-Eleon

[APipm.1]

Hi Eleon!

We are seeing this in all 'Type 2' boards, yes. The current before we set the device to its lowest power mode is around 5mA, so I can not tell if there is an extra 5uA on top of that, the fluctuations in measurement are larger than the offset I'm looking for. The 5uA value is taken by placing the device into its lowest power mode, which consumes around 1.5uA in board type 1, but consumes around 6.5 uA in board type 2. The same shut down commands are passed to all peripherals in both boards, so we know the peripherals are shutting down properly (at least in board type 1).

As for setting the SDO/SA0 and CS pins- I've tried leaving them with pull ups, pull down, and setting them as output direction- logical high. All of these don't reduce my current draw below ~7uA.

BTW, what status are the other pins left at when the LIS2DW12 is turned off, or turned on in low power but with CS low?

I've heard from the other peripheral's manufacturer, and he says all pins are tied high on his device when it is turned off, with a 10K resistor. Could a shared line with two pullups be leaking from one to the other?

Thanks!

[APipm.1]

Hi Again Eleon!

Your query about how many boards of type 2 we're seeing this on got me thinking, and so I went back and pulled a different batch of 'type 2' boards from our order.

These newly tested boards show the expected 1uA current in the lowest possible sleep state, and I had tested 8 of them in two different measuring devices.

It looks like something went wrong in the first batch I was testing. Once I saw two boards showing the same behavior I Immediately assumed this was a design or firmware problem.

Shows me for making assumptions.

Thank you for the help! if you could still comment on the state of the pins in different modes, I'd appreciate it.

[Eleon BORLINI · Accepted solution]

Hi @APipm.1​ ,

thank you for the updates, good to hear that this new batch is now -for some reason- working.

About:

>> BTW, what status are the other pins left at when the LIS2DW12 is turned off, or turned on in low power but with CS low?

It depends on the pin: SDO/SA0 and CS pins are internally pulled up, GND at GND while the other pins are typically in high Z.

-Eleon

[APipm.1]

Thanks for the answer!

Is the common practice for SPI componenet to leave the pull selection to the module which controls the line? (i.e Master controlled pins will be set by the master, and slave controlled pins will be set by the slave?)

I can see why a pull up on the CS will be prudent on the slave's side as well.

[Eleon BORLINI]

Hi @APipm.1​ ,

you might be right, but I believe it should be a design constrain.

-Eleon