IIS3DWB FIFO counter does not decrease when reading.

[Palmering]

Hi,

I'm testing IIS3DWB MEMS accelerometer.

It is set FIFO in continuous mode and FIFO watermark WTM[7:0] = 256.

FIFO threshold interrupt on INT1 pin is enabled.

The uC reads 256 data (7 bytes each) from FIFO_DATA_OUT_TAG as soon as INT goes high. Data is correct. After that the uC reads DIFF_FIFO_[7:0], it has a value >256 so it seems that it didn't decrement. Thus it never interrupts again.

Should the counter DIFF_FIFO_[7:0] decrement every data is read?

Thanks

[TBomb.1]

Hi, if you are running in continuous mode, you might already be in overrun condition and the FIFO has already been refreshed with new samples, keeping the DIFF_FIFO_ at 256.

What if you use the FIFO mode? In this way FIFO stops when filled up to the watermark, and if you then read the FIFO data you should have 0 on DIFF_FIFO_.

Note also that:

In addition, it is possible to configure a counter of the batch events of the sensor. The flag COUNTER_BDR_IA in FIFO_STATUS2 (3Bh) alerts that the counter has reached a selectable threshold (CNT_BDR_TH_[10:0] field in COUNTER_BDR_REG1 (0Bh) and COUNTER_BDR_REG2 (0Ch)). This allows triggering the reading of FIFO with the desired latency of one single sensor. The sensor is selectable using the TRIG_COUNTER_BDR bit in COUNTER_BDR_REG1 (0Bh). As for the other FIFO status events, the flag COUNTER_BDR_IA can be routed on the INT1 or INT2 pins by asserting the corresponding bits (INT1_CNT_BDR of INT1_CTRL (0Dh) and INT2_CNT_BDR of INT2_CTRL (0Eh)). 

https://www.st.com/resource/en/datasheet/iis3dwb.pdf

Tom

[Palmering · Accepted solution]

Hi TBomb.1,

Thank you for your answer.

I'd tried the second option and it ran.

Finally, I decided to read data via DMA, so that the INT1 generates an interrupt in every data instead of using the internal FIFO.