Hello,
I just wanted to inform you that there is a bug in the ST driver for the LSM6DSV16X v3.0.0, available on Github.
Function lsm6dsv16x_fifo_batch_counter_threshold_set is wrongly setting the 2 register values, and for COUNTER_BDR_REG1 it is not ensuring that other bit fields are not changed.
I stumbled upon this after some time trying to get the BDR counter threshold interrupt to work in a prototype, and thought to share it here.
I changed that function implementation to the code below (basically a copy from the LSM6DSOX driver), and it works fine now:
int32_t lsm6dsv16x_fifo_batch_counter_threshold_set(const stmdev_ctx_t *ctx,
uint16_t val)
{
lsm6dsv16x_counter_bdr_reg1_t counter_bdr_reg1;
lsm6dsv16x_counter_bdr_reg2_t counter_bdr_reg2;
int32_t ret;
ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_COUNTER_BDR_REG1,
(uint8_t *)&counter_bdr_reg1, 1);
if (ret == 0)
{
counter_bdr_reg2.cnt_bdr_th = 0x00FFU & (uint8_t)val;
counter_bdr_reg1.cnt_bdr_th = (uint8_t)(0x0700U & val) >> 8;
ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_COUNTER_BDR_REG1,
(uint8_t *)&counter_bdr_reg1, 1);
}
if (ret == 0)
{
ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_COUNTER_BDR_REG2,
(uint8_t *)&counter_bdr_reg2, 1);
}
return ret;
}
Regards,
Rafael
