STM32U5G9 OctoSPI Memory-Mapped Mode with MX35LF1G24AD NAND Flash

[EmbeddedLab]

Hi everyone,

I'm working on a project using the STM32U5G9 microcontroller and trying to interface it with a Macronix MX35LF1G24AD NAND flash via the OctoSPI peripheral.

The goal is to enable memory-mapped mode so the external flash can be accessed as part of the MCU's address space. However, I'm facing some challenges and would appreciate any insights or examples from the community.

Here are my main questions:

1. Is the MX35LF1G24AD NAND flash compatible with OctoSPI memory-mapped mode on the STM32U5G9? Most examples I’ve found are for NOR flash, and I’m unsure if NAND is fully supported in this mode.
2. What are the key configuration steps in STM32CubeMX or HAL to properly set up OctoSPI for this device?
3. Are there any specific limitations or considerations when using NAND flash in memory-mapped mode (e.g., ECC handling, bad block management, page/block alignment)?

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Additional Doubt:

In most OctoSPI memory-mapped examples I’ve seen (typically with NOR flash), the flow looks something like this:

OSPI_RegularCmdTypeDef sCommand = {0};
sCommand.OperationType = HAL_OSPI_OPTYPE_COMMON_CFG;
sCommand.Instruction = READ_CMD;
sCommand.InstructionMode = HAL_OSPI_INSTRUCTION_1_LINE;
sCommand.AddressMode = HAL_OSPI_ADDRESS_1_LINE;
sCommand.DataMode = HAL_OSPI_DATA_1_LINE;
sCommand.DummyCycles = DUMMY_CYCLES;
HAL_OSPI_Command(&hospi, &sCommand, HAL_OSPI_TIMEOUT_DEFAULT_VALUE);

HAL_OSPI_MemoryMapped(&hospi, &memMappedCfg);

However, with the MX35LF1G24AD, it seems that data cannot be read directly from the chip. Instead, you must first issue a Page Read command to transfer data from NAND to the internal cache, and then use a Read From Cache command to access the data. For example:

// Step 1: Page Read (transfer from NAND to cache)
SendCommand(PAGE_READ_CMD, block, page);

// Step 2: Read From Cache (read from internal buffer)
SendCommand(READ_FROM_CACHE_CMD, column_address);

This makes me wonder: Can memory-mapped mode even work with this kind of NAND architecture, where a two-step read process is required?

Any clarification on this behavior or suggestions on how to implement memory-mapped-like access with this flash would be greatly appreciated.

Thanks in advance!

[KDJEM.1]

Hello @EmbeddedLab and welcome to the community;

In order to start with OCTOSPI interface, you need to verify if this device is supported by the interface. The command format and order shared in the device datasheet must be aligned with the command format and order mentioned in the STM32 reference.

Check the STM32U5G9 errata sheet for any known limitations and workarounds.

To configure the OCTOSPI interface using STM32CubeMX, I recommend you to look at AN5050 precisely section "7 OCTOSPI application examples". 

This section provides some typical OCTOSPI implementation examples with STM32L4P5xx/Q5xx products, and STM32CubeMX examples. For that, You can refer to this section and get inspired to configure the OCTOSPI interface.

May Overall FAQs for QUADSPI/OCTOSPI/HSPI/XSPI FAQ can help you. The purpose of this article is to provide external memories tips and tricks, frequently asked questions, and a list for useful link resources. 

Thank you.

Kaouthar

[EmbeddedLab]

Hello @KDJEM.1,

Thank you for your reply, welcome and provided link to FAQ.

I did not mentioned it but I am already able to communicate with the NAND Flash, write data into it and read its content. The complex part is to correctly implement external flash memory mapping because each time that data needs to be retrieved from it, a "Page read" command needs to be sent before actually fetching its content (like shown in "Page Read Cache Flow" diagram and documentation pictures bellow).

How to enable memory mapped and map the entire flash in this situation?

Thank you.