2022-05-05 02:40 AM
Hi all,
We have solution based in a STM32G0B1 microcontroller which needs a very fast communication towards an SPI memory, for doing that, we think in using the dual spi read mode (DREAD), is possible to that whithin this micro? Or we have to go to another micro? Eventually the very approach could be the QuadSPI, but unfornately the STM32G0B1 has only 3 SPI, so our idea is to use the Double Read option (4 bits transfer mode or in this case eventually the 8 bit mode). Is this possible?
Thanks in advance.
Solved! Go to Solution.
2022-06-01 09:53 AM
Hello @Community member,
The QUADSPI is an integrate interface that supports the traditional SPI as well as the Dual-SPI mode which allows to communicate on two lines: one line for chip select, one line for clock and up to four lines for data in and data out.
Thanks to its property of supporting different modes, the QUADSPI interface is integrated on the STM32 devices to fit memory-hungry applications add to high performances guaranteed so it can help you with your application.
For the MCUs presenting this interface, I recommend you referring to the Table 1 & Table 2 of the AN4760. You can also refer to the Configure QUADSPI at maximum speed part of the 7.1.2 section, it helps you get the optimum performances.
Chahinez.
2022-06-01 09:53 AM
Hello @Community member,
The QUADSPI is an integrate interface that supports the traditional SPI as well as the Dual-SPI mode which allows to communicate on two lines: one line for chip select, one line for clock and up to four lines for data in and data out.
Thanks to its property of supporting different modes, the QUADSPI interface is integrated on the STM32 devices to fit memory-hungry applications add to high performances guaranteed so it can help you with your application.
For the MCUs presenting this interface, I recommend you referring to the Table 1 & Table 2 of the AN4760. You can also refer to the Configure QUADSPI at maximum speed part of the 7.1.2 section, it helps you get the optimum performances.
Chahinez.