2019-09-04 12:40 AM
I suppose there are some mistake in Blenrg Code
Statement: * @arg FIFO_LEV_1_64: interrupt when Tx FIFO becomes <= 1/64 full = 1 ... at the line 440 of blueNRG1_uart.c is misleading. In accordance to datesheet instead of "full" should be "empty". In the datasheet for the TXFIFO buffer: 000b: Interrupt when FIFO ≥ 1/64 empty. (page 67 of BleuNRG2 datasheet).
2019-09-12 07:48 AM
Hello Serge,
TXIFLSEL: Isn't it the size of the bitfield ? The value 3 seems OK to me.
As for FIFO empty and "whole stuffs sent, comprising last stop bit", there seems to be two distinct interrupts (See 3.9.2.6 page 60 on DS12166 Rev 5).
2019-09-12 09:49 PM
Sorry I was wrong about TXIFLSEL. But unfortunately, I can't change/edit or delete this my message.
2019-09-13 02:00 AM
No problem. Anyway, the provided code is often much more examples (hence bottom-up design) you need to reachitect and harden to get production quality code. For instance: no timeouts, assumptions on values, hidden limitations, pushdowns, etc... (and unfortunetly factored with various proprietary bloatware IDE's (read: "carefully designed to obfuscate things") so extraction/cleanup pass to start with).
One really good point is that macro names and fields matches the datasheets so it eases reading and understanding.