2020-10-16
09:31 AM
- last edited on
2023-12-06
05:41 AM
by
Laurids_PETERSE
I am outputting audio over I2S at 8k with a 128 sample buffer. I was getting timing issues so I turn on an LED on the Half way callback and turn it off on the complete callback. I expect a 50% duty cycle. But I get the output below on my scope. Anyone else see this or know what can cause it? The overall time is about right for a 256 sample buffer at 8k but the timing is wrong
2020-10-16 11:32 AM
Seems to be that the Complete callback is being called immediately after the Half Complete callback every time
Anyone have any ideas why this should happen. I derived my code from the DK - the DK does work however with the expected 50:50 duty cycle
2020-10-16 01:32 PM
Your image doesn't show up. Maybe slow down the rate and see if it works as expected. Maybe you're doing too much within the interrupt.
2020-10-16 01:34 PM
Thanks. I have tried different rates. I actually looked closer at the standard DK code from ST and that fails also. I'm doing nothing in the interrupt except turning an LED on on one callback and off on the other. The Half Complete callback fires immediately before the Complete callback on DMA transfer for SPI and I2S when in circular mode
2020-10-16 01:34 PM
or info - this is on a BlueNRG-LP