SPC5Studio: EMIOS register definitions for SPC56EC wrong?

[Tim Tashpulatov]

Posted on November 09, 2017 at 08:15

I want to use EMIOS and PWM for SPC56EC74. When debugging the code for Channel 0, I can see that channel 9 is being initialized instead.

Looking into 

the xpc56ec.h file, EMIOS section, the UCDIS Disable Channel Register is being described starting at (Base+0x000F), whereas in the datasheet it is said to be at (Base+0x000C).

Is the xpc56ec.h header not compatible with SPC56EC74?

The code:

pwm_lld_init (); 

pwm_lld_start (&PWMD1, &pwm_config_pwmcfg);

pwm_lld_enable_channel (&PWMD1, 0, PWM_PERCENTAGE_TO_WIDTH(&PWMD1,5000));

The header in question is taken from the following plugin:

com.st.spc5.components.platform.spc56ecxx_rla_1.0.0.201707271939\component\lib\include\xpc56ec.h

Regards

Tim

#emios #spc56xx

[Erwan YVIN · Accepted solution]

Posted on November 09, 2017 at 10:00

Hello Tim ,

ihave checkedthe header file

 union { /* Output Update Disable (Base+0x0008) */
 vuint32_t R;
 struct {
 vuint32_t OU31:1;
 vuint32_t OU30:1;
 vuint32_t OU29:1;
 vuint32_t OU28:1;
 vuint32_t OU27:1;
 vuint32_t OU26:1;
 vuint32_t OU25:1;
 vuint32_t OU24:1;
 vuint32_t OU23:1;
 vuint32_t OU22:1;
 vuint32_t OU21:1;
 vuint32_t OU20:1;
 vuint32_t OU19:1;
 vuint32_t OU18:1;
 vuint32_t OU17:1;
 vuint32_t OU16:1;
 vuint32_t OU15:1;
 vuint32_t OU14:1;
 vuint32_t OU13:1;
 vuint32_t OU12:1;
 vuint32_t OU11:1;
 vuint32_t OU10:1;
 vuint32_t OU9:1;
 vuint32_t OU8:1;
 vuint32_t OU7:1;
 vuint32_t OU6:1;
 vuint32_t OU5:1;
 vuint32_t OU4:1;
 vuint32_t OU3:1;
 vuint32_t OU2:1;
 vuint32_t OU1:1;
 vuint32_t OU0:1;
 } B;
 } OUDR;
 union { /* Disable Channel (Base+0x000F) */
 vuint32_t R;
 struct {
 vuint32_t CHDIS31:1;
 vuint32_t CHDIS30:1;
 vuint32_t CHDIS29:1;
 vuint32_t CHDIS28:1;
 vuint32_t CHDIS27:1;
 vuint32_t CHDIS26:1;
 vuint32_t CHDIS25:1;
 vuint32_t CHDIS24:1;
 vuint32_t CHDIS23:1;
 vuint32_t CHDIS22:1;
 vuint32_t CHDIS21:1;
 vuint32_t CHDIS20:1;
 vuint32_t CHDIS19:1;
 vuint32_t CHDIS18:1;
 vuint32_t CHDIS17:1;
 vuint32_t CHDIS16:1;
 vuint32_t CHDIS15:1;
 vuint32_t CHDIS14:1;
 vuint32_t CHDIS13:1;
 vuint32_t CHDIS12:1;
 vuint32_t CHDIS11:1;
 vuint32_t CHDIS10:1;
 vuint32_t CHDIS9:1;
 vuint32_t CHDIS8:1;
 vuint32_t CHDIS7:1;
 vuint32_t CHDIS6:1;
 vuint32_t CHDIS5:1;
 vuint32_t CHDIS4:1;
 vuint32_t CHDIS3:1;
 vuint32_t CHDIS2:1;
 vuint32_t CHDIS1:1;
 vuint32_t CHDIS0:1;
 } B;
 } UCDIS;�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?

The comments are false

it should not be :

/* Disable Channel (Base+0x000F) */�?

it should be 0x8 +x04 = 0xC

/* Disable Channel (Base+0x000C) */�?

i am creating an ER to correct the header file and to integrate it in the last components version

Best regards

Erwan

[Tim Tashpulatov]

Posted on November 09, 2017 at 11:08

Hello Erwan,

Thank you for prompt reply. Indeed, it seems to be the comments issue, as the code is working as it should. I yet have to understand the reason behind EMIOS group 0 using channels starting from 9 and up, but this may be the way PWM LLD works.

Regards

Tim