SPC560D40L1 - ADC does not finish sampling

sp · ‎2014-04-03

Posted on April 03, 2014 at 12:21

Hi,

I'm trying to setup an analog conversion on SPC560D40L1. I activated the ADC in HAL configuration, defined a adc-conversion-group that consists of channel 0 (ADC1_P[0] on Pin PB4).

The ADC does not finish the sample. The ADCD2 state is ADC_ACTIVE and the ADC_MSR.ADCSTATUS is 0x4(Sample). The values in the buffer stay unchanged.

My Settings for the conversion group ''Precision'':

- Linear, Max Sequential: 4

- Watchdog functions are all disabled

- Channel Settings: Inital: 0, Number of channels: 1

- Timing: CTR0_INPLATCH = 1, OFFSHIFT = 0, INPCMP = 2, INPSAMP = 9, CTR1,2 the same

- No callbacks are used

In the eDMA_MUX_Settings, ADC uses DMA2.

My Programm looks like this:

int main(void)

{

uint16_t adcBuffer[4];

componentsInit();

osalIsrEnable();

adcStart(&ADCD2, NULL);

adcStartConversion(&ADCD2, &adc1_group_precision, &adcBuffer[0], 4);

while(1)

{

}

The registers of ADC and eDMA seems to be right, the Clock Settings should be right, I can't find register ME_PCLT33 in the PLS-Debugger (32 and 44 are there).

Thanks for help.

StefanP

By the way, ADC-Channel 44 can not be selected in the Conversion Group Setup.

Erwan YVIN · ‎2014-04-04

Posted on April 04, 2014 at 14:42

Hi Stefan ,

your application is working well.

1) Just 1 issue in your loop.

While(1) {} is ''skipped'' by the hightec compiler.

os-less is exited and you lose your end of conversion by DMA.

please add osalThreadSleepMilliseconds(500); in your loop

while(1)

{

osalThreadSleepMilliseconds(500);

0x000024D6: 70 60 01 F4 E_LI R3,0x1F4

0x000024DA: 79 FF FF 67 E_BL osalThreadSleep (0x00002440)

0x000024DE: E8 FC SE_B 0x000024D6

}

After the state of ADC high level driver is well ADC_READY ;)

2) About ME_PCLT33 :

generally , to access to all registers you can use watch variable in PLS debuggers

copy-paste

((ME_tag*)(0xC3FDC000)) in Watch windows

Non-Applicable for Reserved memory. (cf Reference Manual)

3) Concerning the channel 44 : i have checked in the reference manual .. in the D Family there are only 12 standards channels from 32 to 43.

i am waiting for your feedback

Best regards

Erwan Yvin

Hi,

I'm trying to setup an analog conversion on SPC560D40L1. I activated the ADC in HAL configuration, defined a adc-conversion-group that consists of channel 0 (ADC1_P[0] on Pin PB4).

The ADC does not finish the sample. The ADCD2 state is ADC_ACTIVE and the ADC_MSR.ADCSTATUS is 0x4(Sample). The values in the buffer stay unchanged.

My Settings for the conversion group ''Precision'':

- Linear, Max Sequential: 4

- Watchdog functions are all disabled

- Channel Settings: Inital: 0, Number of channels: 1

- Timing: CTR0_INPLATCH = 1, OFFSHIFT = 0, INPCMP = 2, INPSAMP = 9, CTR1,2 the same

- No callbacks are used

In the eDMA_MUX_Settings, ADC uses DMA2.

My Programm looks like this:

int main(void)

{

uint16_t adcBuffer[4];

componentsInit();

osalIsrEnable();

adcStart(&ADCD2, NULL);

adcStartConversion(&ADCD2, &adc1_group_precision, &adcBuffer[0], 4);

while(1)

{

}

The registers of ADC and eDMA seems to be right, the Clock Settings should be right, I can't find register ME_PCLT33 in the PLS-Debugger (32 and 44 are there).

Thanks for help.

StefanP

By the way, ADC-Channel 44 can not be selected in the Conversion Group Setup.

sp · ‎2014-04-04

Posted on April 04, 2014 at 22:05

Hi Erwan,

no, this doesn't solve the problem. As you can see in the screenshot, acd is still sampling, even after 20s and no adcBuffer is written. I don't know where I have to search.

Concerning the channel 44: my reference Manual shows PB12 as ADC1_S[12] and on the image on Page 656 (Doc ID 16886 Rev 6) there are ADC1_S[0] (Ch 32)... ADC[12](Ch 44).

Regards

StefanP

Erwan YVIN · ‎2014-04-07

Posted on April 07, 2014 at 16:56

Hello Stefan ,

i am sending my test application by attachment.

Could you send me your test application ?

i do not reproduce this issue cf screenshot

There is no CDR . good catch, i suspect that it is an error in the reference manual.

I am going to check with ADC experts on the small bolero.

Best regards

Erwan

________________

Attachments :

SPC560Dxx_OS-Less_ADC_Test_Application_Stefan.zip : https://st--c.eu10.content.force.com/sfc/dist/version/download/?oid=00Db0000000YtG6&ids=0680X000006I0IT&d=%2Fa%2F0X0000000bZJ%2Fv4hfhe27n2BR0ta81O6gnKk3zIWoAZxdRUT9j_U3jk8&asPdf=false

Erwan YVIN · ‎2014-04-08

Posted on April 08, 2014 at 10:30

Hello Stefan ,

For your information , an error report has been created for the reference manual. (Bolero 256k)

In SPC5Studio side, I am checking if the CDR44

in the reserved part

is accessible.

If yes, we will add the channel in the SPC5Studio plugins (in the next release)

i am waiting for your feedback about your ADC Applications

Best Regards

Erwan

sp · ‎2014-04-08

Posted on April 08, 2014 at 15:29

Hi Erwan,

I tried your code. When I import the Projekt I get the Information:

Configuration settings ''dma_mode'' not found in instance of component ''org.chibios.spc5.components.hal.platform.spc560xx:[Element <adc_settings />]''

I'm using SPC5Studio 2.0.0.

I copied your settings to my Project and got the same Problem. The ADC1-registers have the same values as on your screenshot, but ADC stays sampling.

Can I send you my code via email, I'm not shure that I have removed all information (costumer/project).

Thanks,

StefanP

Erwan YVIN · ‎2014-04-10

Posted on April 10, 2014 at 11:17

Hi Stefan,

My email address is erwan.yvin@st.com

You can send me your application after export by email.

BR

Erwan

Erwan YVIN · ‎2014-04-10

Posted on April 10, 2014 at 11:43

Hello Stefan ,

For dma mode, it is just a warning ''dma_mode''..

because , the next official ADC drivers could add the possibility to enable or disable DMA.

(Available in may 2014)

1) After the warning

2) Just Save the configuration

3) Clean the project

4) Regenerate

5) Build

Anyway , send me your application .. i will try with your application ;)

Best Regards

Erwan YVIN