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Hi, I'm evaluating a solution for a 1 ms reading using the SDADC driver provided with the SPC Studio (SPC58NE). I found this check in the code, that sometimes causes a missing reading. I add a comment with the SFR register that I'm currently using.

VBOSC.1
Associate
uint8_t sdadc_lld_read(SDADCDriver *sdadcp, float* converted_value) {
 
  int16_t data;
  uint8_t return_value = SDADC_DATA_NOTVALID;
 
  /* check if valid data is available */
  if (sdadcp->sdadc->SFR.B.DFEF == 0U) /* <- Check if the FIFO is not empty */
  /* if (sdadcp->sdadc->SFR.B.CDVF == 1U) */ /* <- Check if data is valid */
  {
    /* read converted data */
    data = (int16_t)((uint16_t)sdadcp->sdadc->CDR.R);

Is it right to check the DFEF (which is related with the FIFO) and not the CDVF (valid data)?

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1 ACCEPTED SOLUTION

Accepted Solutions
Erwan YVIN
ST Employee

Hello ,

DFED in the Data Fifo Empty Flag.

This field is asserted when there is no data word in the FIFO.

0 Data FIFO is not empty.

1 Data FIFO is empty.

What is the clock of SDADC ?

for 1ms , maybe it is better to check if the data is vali or invalid.

cf chapter Sigma-Delta Analog-to-Digital Converter (SDADC) Digital Interface

Do not hesitate to add some additional checks in order to put the driver more robust.

Best regards

Erwan

View solution in original post

2 REPLIES 2
Erwan YVIN
ST Employee

Hello ,

DFED in the Data Fifo Empty Flag.

This field is asserted when there is no data word in the FIFO.

0 Data FIFO is not empty.

1 Data FIFO is empty.

What is the clock of SDADC ?

for 1ms , maybe it is better to check if the data is vali or invalid.

cf chapter Sigma-Delta Analog-to-Digital Converter (SDADC) Digital Interface

Do not hesitate to add some additional checks in order to put the driver more robust.

Best regards

Erwan

VBOSC.1
Associate

Hi Erwan, thank you for the reply.

I found in this project this solution:

  1. SDADC is inited and the "start_conversion" is called;
  2. Then, the sdadc_lld_read is called to get the data into a task (no period, is called continuously, I will check the clock);
  3. I found that, even with the FIFO disabled, the DFED could change. Inside the "sdadc_lld_read", this flag is always checked so we could lost sometimes the data when the FIFO is empty. We have to change the logic and check instead the CDVF, and it is working good...now we are testing this change. In my opinion there must be a configuration to keep the DFED to never be empty (as I expected: no one is clearing the FIFO).

Probably I'm missing something, I will check the suggested chapter - hey the link is not working (if it's a link) :)