VN9D5F20F SPI error problem

[FPros.1]

Hi everyone,

I am implementing the communication between MCU SPC582B and High side driver VN9D5D20F.

SPI signals seem fine to me, see next image:

Spi Clk frequency = 625kHz  (range is 0Mhz to 8Mhz)
CS transaction time = 71us
Time between bytes = 7us

Transaction 1 = read CTRL (en = 1, parity = 1, GSBN = 1)
Transaction 2 = read SOCR (all zeroes, GSBN = 1)
Transaction 3 = GSB = 20h (SPIE = 1)

On the third transaction, I can't understand why reading SOCR register cause the driver to throw the SPI error (clk count is adequate and SDI is not stuck.

I can't figure out what I am doing wrong.

Any help would be very much appreciated.

Thanks,

FP

[FPros.1 · Accepted solution]

I was not specifying correctly the parity bit during transmission.

The parity bit had to be computed based on the first 23 bit of the frame.

Regards,

FP

[Ollie]

Hi,

I'm encountering an issue when working with SPI communication and writing to specific registers. Writing to register 0x13 returns the correct response of 0x80, 0x0F, 0x01, which looks good, but I’m not observing any output on any of the channels.

The problem becomes more complex when I write to registers 54 and 53 followed by register 13. In this sequence, writing to register 13 results in a return value that triggers the 0x20 SPIE bit, indicating an error, however the return from 54 and 53 are 0x80 and the values i would expect.

My SPI settings are as follows:

• Clock frequency: 625 kHz (within the 0 MHz to 8 MHz range)
• CS transaction time: 71 µs
• Time between bytes: 7 µs

Have you experienced similar behavior or have insights into why writing to register 13 after 54 and 53 results in this error? Any advice on specific sequences, timing, or additional configurations needed would be greatly appreciated.

Thanks for any help you can provide!