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Hello STM32 Community, I am facing a persistent "Target no device found" error when trying to program an STM32L073CZT3 custom board using a Nucleo-L073RZ as an external ST-LINK (CN2 jumpers removed). Hardware Setup: MCU: STM32L073CZT3 (custom PCB) Debugger: ST-LINK V2-1 (Nucleo-64) Connection: 5-wire SWD (SWDIO, SWCLK, GND, NRST, VDD_Sensing) Power: External SMPS providing 3.3V (Common Ground established between SMPS and ST-LINK). The Issue: While the ST-LINK pins show correct voltages when floating, the SWDIO (PA13) pin drops to 0V the moment it is connected to the target board. Pin 1 (VDD Sense): 3.3V Pin 2 (SWCLK): 3.29V Pin 4 (SWDIO):  (Measured 2.9V on ST-LINK side connection) Pin 5 (NRST): 3.3V Troubleshooting performed: Verified continuity; no physical shorts found between PA13 and GND. Attempted "Connect Under Reset" and "Hardware Reset" at 480 kHz. Schematic Check: I have a 10uF capacitor (C17) on the NRST line—could this be preventing the debugg

Dear ST Technical Support Team,I am currently using the ST1S10PHR buck converter in my custom PCB design to convert 12V input to 5V output.However, the regulator is not switching to the expected 5V output. The measured output voltage remains around 0.79V.Below are the measured and design details:Input Voltage: 12VVIN_SW and VIN_A pins: Confirmed 12V presentEN (INH) pin: 12V present (device enabled)Expected Output Voltage: 5VMeasured Output Voltage: ~0.79VFeedback Resistors: R1 = 11kΩ, R2 = 2kΩInductor: 3.3µHSwitching frequency: Internal 900kHz (SYNC connected directly to GND with short trace)GND and EPAD connected to ground planeOne concern in my PCB layout is that the SW pin to inductor trace length is approximately 47mm. Although the inductor is placed near the IC, the copper routing from SW to the inductor became long due to layout constraints.The board powers up correctly, and all input pins measure properly, but the output remains close to the feedback reference voltage (~0.8V) an

Hi,We are building Linux for STM32MP157D using Buildroot, and we are experiencing an issue where the boot process sometimes does not proceed from BL2 to OP-TEE, and sometimes OP-TEE does not proceed to U-Boot.Occasionally, the kernel does boot successfully.Could this be caused by incorrect DDR3 controller settings? We are using a custom board.If so, would compiling the STM32DDRFW-UTIL source code and using it in engineering mode be the right solution?I have read that for some chips it is possible to perform automatic tuning and receive the optimal configuration as a result.Is this possible in this case? If not, what is the proper method to determine the correct DDR controller settings?If DDR is not the issue, do you have any other suggestions?For testing with DDR-UTIL, I see that there is no development board listed for the 157D series, as the utility supports "STM32MP157C-EV1_DDR_UTILITIES_A7".If we order the "STM32MP157D-EV1", will I be able to run DDR tests on it to compare with our

I need support for the design of STM32WL30XX PCB Antenna. Are there reference designs available for the PCB antenna?Specifications:Two layer board Output power 10dBm in the 868MHz band.   

Hello,   Is there a setting in MX2 to enable/disable timer freezing during debugging? If not, what HAL APIs can be used for this purpose?   Thank you, Gil

Hi Apologies in advance if these are daft questions, however I'm trying to put together a development kit for the SR5E1E5 . I have found the SR5E1-EVBE5000P evaluation board, but need a debugger to use with it.  I assume that the ST-LINK/V2 is compatible but can someone please confirm this?  Also can the Stellar Studio All in One be used with this combination? The SR5E1-EVBE5000P has a USB connector can I assume this does not support debugging via Stellar Studio All in One?We already have the SPC5-UDESTK, but I assume that this is not compatible with the Stelar series of micros? Thanks in advance.

NUCLEO-F767ZI I'm trying to use the LwIP middleware which I have enabled in MX. First I'm trying to check if an ethernet cable is attached or not. I have setup UART3 to use printf (which works as expected) I've set the callback in lwip.c to print when the cable is removed or plugged in or so I thought but I get no message when I connect or disconnect the cable. The LEDs on the socket light up when the cable is connected, so the board at some level does see the cable. What am I missing here? EDIT:: LWIP_NETIF_LINK_CALLBACK was enabled in MX // In main.c MX_LWIP_Init(); /* USER CODE BEGIN WHILE */ while (1) { MX_LWIP_Process(); /* USER CODE END WHILE */ /* USER CODE BEGIN 3 */ } /* USER CODE END 3 */ // In lwip.c the callback function that is registered in MX_LWIP_Init() static void ethernet_link_status_updated(struct netif *netif) { if (netif_is_up(netif)) { /* USER CODE BEGIN 5 */ printf("Cable connected\r\n"); /* USER CODE END 5 */ } else /* netif is down */ { /* USER C

Hello, I have a simple CubeMX project with the STM32N6 MCU, and I cannot seem to be able to uncheck the FREERTOS option from the FSBL to move it to the Application.  Is there something I am doing wrong? Thank you 

Hello,   I configured a timer in STM32CubeMX2 to use 2 channels (HAL_TIM_CHANNEL_1 and HAL_TIM_CHANNEL_3). After the mx_system_init() I use the following code: hal_tim_handle_t *htim5 = mx_tim5_gethandle(); if (HAL_TIM_OC_StartChannel(htim5, HAL_TIM_CHANNEL_1) != HAL_OK) { return (-1); } if (HAL_TIM_OC_StartChannel(htim5, HAL_TIM_CHANNEL_3) != HAL_OK) { return (-1); } if (HAL_TIM_Start(htim5) != HAL_OK) { return (-1); }  The first channel starts as expected, but when I attempt to start the second channel the code causes an assert in HAL_TIM_OC_StartChannel: /* Check and update the channel state */ ASSERT_DBG_STATE(htim->channel_states[channel], HAL_TIM_OC_CHANNEL_STATE_IDLE);   Do I need to do anything different?   Regards, -Gil

The entry for address 0x1FFF7838 in Table 17 ( Organization of option bytes) shows FLASH_PCROP1ASR as the "Corresponding option register" - it should be FLASH_PCROP2ASR.

   Trying to Interface ADS1293 with STM32U5 for 3-Lead ECG – Need Help with Lead II Data Hi STM32 Community :waving_hand:, We’re trying to build a 3-lead ECG signal acquisition setup using the ADS1293 analog front-end connected via SPI to an STM32U5G9ZJT6Q microcontroller. The goal is to capture and plot Lead I, Lead II, and derive Lead III using TouchGFX.  What’s Going Well: We are able to receive and plot clean ECG data for Lead I (RA - LA) using CH1 of the ADS1293. SPI communication is stable, and the plotting is handled through TouchGFX without lag. Sampling is working at 500–1000 Hz using a DRDY-based interrupt routine. What We’re Struggling With: When we try to configure CH2 for Lead II (RA - LL), the data appears noisy, flat, or unstable. We’re using the same initialization and acquisition process for CH2 as we did for CH1, but the result is not usable. For Lead III, we are trying to derive it in software using: Lead III=Lead II−Lead&nbsp

hello ST Community,There's an STM32 board in a USB pen drive format with a small flash memory capacity and only a few pins (3-5 pins) for UART serial communication. On this STM32 board, inside the USB pen drive, I can program the dedicated software for serial communication.If it exists, can you tell me the model and serial number? I can't find it online.Thanks for the information.

We will design a layout for the VD55G1 Promodule with Image read out over I3C. Alternative there is also a VD55G4 camera with an additional SPI image read out. Is it possible to get the pin assignment for the new VD55G4 promodule ?

While I was experimenting with the 'L476 Disco, the RM wording goes across multiple families, so it may be relevant to most/all of them. In particular, for Shutdown mode (which is supposedly the lowest-VDD-consumption mode), the RM says: What does "switch to Backup domain is not supported" mean, exactly (assuming VDD and VBAT have separate sources)?  as soon as Shutdown mode is entered, RTC (backup domain) is switched to VBAT even if VDD is present, potentially draining the VBAT source (battery, capacitor) in Shutdown, while VDD is present, RTC is powered from VDD; but when VDD is removed, RTC is *not* switched to VBAT, resulting in backup-domain reset and/or RTC corruption in Shutdown, while VDD is present, RTC is powered from VDD; but when VDD is removed, most of the time the switch flips to VBAT as expected, but this is not reliable and sometimes RTC corruption occurs in Shutdown, it's unpredictible, what is the backup-domain switch state, even while VDD is present These are

I’m designing a board using the STM32U083MCT6TR, and my system supply voltage is VDD = 1.8 V.The design does not use USB at all. The datasheet specifies that VDDUSB normally requires 3.0–3.6 V for USB operation, but it’s not fully clear what the correct connection is when USB functionality is not needed. My question:What is the recommended way to handle the VDDUSB pin when USB is unused and the MCU is powered at 1.8 V? Should VDDUSB be tied to VDD (1.8 V)? Should it be left unconnected? Or is another configuration required? If anyone has experience with the STM32U0 series or clarification from ST, I’d appreciate the guidance. Thanks, -Tal

Hi everyone,I’m currently working on a project involving LR-FHSS and I’d like to know whether there are STM32-compatible end devices and gateways that already integrate LR-FHSS-capable radio chips.From what I’ve found so far:End Devices (sensor/node): They must use a chip from the SX126x family.Gateways: They need to be based on the SX1302 or SX1303.Before I start designing custom hardware, I’d like to confirm whether there are existing commercial end devices or gateways that already include these chips with LR-FHSS support.If anyone has experience with this or can recommend specific hardware, I would really appreciate it.Thanks!

This is probably an old hat to most of you here but I'm facing this problem momentarily:Using an STM32F103CBT6 (Blue Pill) where GPIOB Port is used already with the following PB3 - SPI1_SCKPB5 - SP1_MOSIPB6 - Some Interface Function (OUTPUT)PB7 - Some Interface Function (OUTPUT)   I want to use PB0, PB1, PB4, PB8, PB12,PB13,PB14,PB15 for a keyboard matrix scan and outputa running pattern to these pins. Writing the bits should be nondestructive what the remaining bits is concerned. At the back of my mind I recall something like BSRR, but could someone help me to get on the right track?I'm using HAL in this app (under STM32CubeIDE).

Hi, I am working with the SBSFU_Boot on the STM32U5A9 chip. After the SBSFU_Loader has written the update image into internal memory, a reset happens in order for the SBSFU_Boot to write the image to be booted. When performing the update, it ends up in a process where it has to do some encryption. The SAES engine is initialized successfully, and then AES_Encrypt is called. This keeps on failing because a read error is reported in the SAES->SR reports a read error upon enabling the SAES peripheral. It should be noted that the initialization and encryption sequence is strictly followed per instructions in RM0456 Rev 6 sections 50.4.4 (Initialization of SAES) and 50.4.8 (ECB/CBC encryption sequence) respectively. What am I missing?

@FBL Can you explain me about buffer descriptor table (BDT)? Is it fixed?I have got behavior that I can't explain.Dumping packets on host I got wrong data. Length is ok, but data is wrong.In BDT I wrote correct address and length. Data wrote in pma (adress that is in BDT) is correct.But when I stop in debugging address in BDT is changed. As I think in BDT there is a place for each endpoint (or it is like cyclic buffer?)What I found if I set break point with "if" condition, just before sending address in BDT is OK, and data on host is OK. It seems to me that I am working incorrectly with BDT.

Split from WiFi or WiFi+BT modules architecture and parts recommendations as that's really a separate question!Thank you @Andrew Neil I didn’t explain myself very clearly. The part I’m mainly interested in is the audio side — specifically, a microcontroller with some kind of audio I/O capability, such as microphone input and speaker output, for recording (and then saving to uSD - perhaps using DMA if it makes sense). I’ve never worked with microcontrollers for audio recording before, so if such micro is not available, I’m also open to a low-cost solution/architecture that uses external components.Thank you

The ST1S06xx datasheet (https://www.st.com/resource/en/datasheet/st1s06.pdf) contains an error: Figure 10 "Input voltave vs output voltage" has the axes labels swapped:A correct version of the Input voltage vs output voltage characteristic can be found in figure 7 of Application Note 2371 https://www.st.com/resource/en/application_note/an2371-st1s06-high-frequency-synchronous-buck-converter-stmicroelectronics.pdf : The datasheet is also missing details on a crucial characteristic: output voltage vs current. In my circuit I have R1=18k, R2=5.6k. Nominal output should be Vout = 0.8V*(1+18/5.6). With a load of 600mA I measure Vout = 3.36V; increasing the load to 800mA, Vout = 3.16V. Another crucial characteristic that's missing detail is dropout voltage: the only indication is figure 11 mentioned above, which suggest for a 1.2V / 1.5A output the dropout voltage is approx 1.1V, but there's no indication of how that changes with input/output voltage or current.

(I tried to submit a ticket but the system seems broken, giving an obscure error about an incorrect zip code).I need to confirm which version of STM32 is placed on a board. There are two versions, GP and PD. The datasheet does not really specify how the top marking is different for the two versions.    Any ideas?Thanks, Pete

I have a project that is using custom hardware with a STM32G0B1CBT6 processor.  The code is developed using STM32CubeIDE and STM32CubeMX.  However, there are times when I am unable to run a debug session and I'm seeing (very) occasional Hard Faults.I have a diagnostic serial port and have successfully modified my Hard Fault Handler to dump additional information out that port.So what I'm after is some code that can read registers and/or the stack to provide additional information that I can use (along with the map file, etc) to determine where my Hard Fault is happening.Can anyone point me in the right direction?  All my searches have shown me code that references registers I can't seem to find in the docs.Thanks.  

Hi,I am setting up SBSFU on our STM32H750. I want to test the RDP and WRP security protections.Steps taken so far:I have enabled WRP and RDP Level 1 by setting the option bytes through cubeprogrammer and enabling SFU_WRP_PROTECT_ENABLE & SFU_RDP_PROTECT_ENABLE in app_sfu.hI have enabled SFU_TEST_PROTECTION in app_sfu.h Note:There are several test cases in sfu_test.c that I am using. The tests in questions are attached below:TEST_ERASE_FLASH is failing.  Output:I am not sure why this would be. Does anyone have any advice? 

Hi everyone,I’m currently working with the CR95HF and looking into using the provided DLL (CR95HF.dll) for PC-side communication.From the documentation and software packages I understand that a DLL is provided to interface with the CR95HF demonstration board (). However, it seems this DLL was originally built for older environments and is typically installed in x32 systems, which suggests it may be a 32-bit library.I searched the community and found a previous discussion where someone asked about x64 compatibility ( Solved: CR95HF DLL for x64 - STMicroelectronics Community ) and was provided with source code instead of a precompiled DLL.So my questions are:Is there now an official x64-compatible version of the CR95HF DLL available?Or is the recommended approach still to request/use the source code and rebuild the DLL for x64 systems?If rebuilding is required:Is there any official guidance or updated project for generating a 64-bit version?Thanks in advance for your help!