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This is mostly a post to help people who try to google this later since I couldn't find anything. If you look at AN2606 table 197, it lists the minimum startup time for the bootloader on a bunch of different STM32 microcontrollers. For some reason, just two MCUs have "NA" listed including the chip I'm currently working with - the STM32L4R. So if anyone is wondering, my testing has shown that it takes ~90ms from reset/powerup to when the chip will ACK the 0x7F message on USART.I am curious though, does anyone know why no time is listed for these chips?

Hi everyone, I'm currently experiencing a strange crash on a STM32G473 and I'm a bit stumped on how to debug it. First the crash: The system is a STM32G473 running FreeRTOS V10.5.1. I have a simple FDCAN ISR which takes the incoming CAN frames and pushes it to a FreeRTOS queue for use in user space in a task; nothing fancy except this, just transforming the data to a nicer structure and clearing the FIFO and so on. During high bus loads however, the FDCAN ISR will sometimes fire during a FreeRTOS context switch. When it does, the system crashes, which is a problem in and of itself, but the main issue is that the NMI is triggered and not the Hardfault. SRAM Parity is enabled, but not Clock Security. Attached is the NMI Handler. I'm checking every bit in HFSR, CFSR, AFSR, The parity error bit and the flash ecc bit and even the css bit are checked. I'm stepping through the function and checking if anything could have triggered the NMI. None of the relevant bits are set to 1 howe

Recently, I have been working on a project that intends to utilize the v9.x bootloader on an STM32L471VGT6 through the SPI 2 port. When utilizing the write memory command, I would find that the STM32L4 would occasionally have 0xFFFFFFFFFFFFFFFF written to its flash rather than the data I had requested. The frequency of this error increased the higher the baud rate of the SPI was and I found the issue was also much more prevalent in polling mode vs DMA mode. I happened to be reading through AN2606 and found in the version history for the L496 that theres is a known limitation on that processor with SPI writes. The behaviour listed was identical to what I was observing on the L4 and thankfully, the listed WA1 also solved the issue for the L4. Thus, I believe that the SPI write failure described for the L496 bootloader also exists on the L47 family and is currently undocumented. 

I am working on a STM32H723 microcontroller and I am trying to use and SPI communication in mixed mode, i.e. normal and DMA.The reason I need this is because I have a third party software stack for a device that is set up in a certain way, and it cyclically has to send small packets before sendind a big packet of user data. The application requires hard real-timeness so I want this exchange to be as fast and as little CPU blocking as possible. Considering these transfers must follow a certain order and that the stack I'm using is not organised as a state machine, I can only send the little packets in blocking mode, but then I'd like to send the big packet in DMA mode. The problem I'm encountering is that after using once the SPI transfer in DMA mode, the blocking transfers don't work anymore. When debugging I see that the periphery becomes permanently busy when trying to perform a normal transfer after using it in DMA mode in the previous cycle. I'd like to know whether it's

Hello, I have a question about LWIP functionality.I'd like to know if it's possible to redirect a tcp request received on the pppos interface, to a device that is connected onto the ethernet interface and listening on the desired port.Thanks in advance!

 I am working on a prototype board using the STM32H725VGT, based on an existing custom board where LWIP/RTOS Ethernet is already working. Since I have a preference to keep the same MCU for the next design, I am evaluating its ability to support an 8-bit wide data bus with a strobe clock and DMA write-only transfers. I have a few specific questions:1. OctoSPI Availability:• In STM32CubeIDE, the OctoSPI peripheral is disabled for this MCU/package.• I could not find a clear reason in the datasheet or reference manual. Why is it unavailable, and is there any way to enable it?2. FMC Peripheral for 8-bit Bus:• The Flexible Memory Controller (FMC) seems to allow different configurations depending on the package.• Some STM32H725 variants have different FMC modes available. Why do FMC options differ between STM32H725 packages?• Would LCD mode be a viable alternative to achieve a DMA-driven 8-bit wide write bus with a strobe clock?3. Alternative Solutions:• If OctoSPI is unavailable an

Hi community!I'm using Touchgfx 4.24.1 with a STM32H753ZIT6, integrated to a 1024x600 (RGB565) display. We use double frame buffer in an external SDRAM (parallel) with DMA2D enabled. This is a OEM custom board design for us, so the hardware is already validated.Application is running with FreeRTOS.My question to this thread is about the Modal Window.We design a pop up question in our application that have been a weird behaiviour.Always I call the popup.show() or popup.hide(), the entire screen is redraw. I believe it's true, specially if we apply a shade color with shade alpha higher than 0, am I correct?I do not use the popup.show() or popup.hide() frequently, it only are used after an button callback.The weird behavior using Modal is when it show or hide, affect another widgets in my view, specially the TextArea. Sometimes the a character disappear or just swap to '?'.About the '?', I double check the Typographies is everthing is OK, otherwise with/without the modal I always wil

Im building some phase shifting control sensing for a Dual Active Bridge.Im using TIMA and TIMD (shown in pictures) in retrigerable single mode, both signals are triggered by sepparate CR from the master timer. https://community.st.com/t5/stm32-mcus-products/synching-hrtim-s-tima-and-timb/td-p/770972Im trying to trigger ADC measurements only on the high side of the PWM but im getting low side aswel.:( , i dont want those 0s there  Is there any way of using PWM in centered mode and also just triggering ADC measurements in high PWM period?

Hi,I am encountering a hard fault on my STM32F407ZG when using snprintf(). We are using FreeRTOS for the development.The system resets due to a precise data access violation (PRECISERR).Below is the fault status: HFSR: 0x40000000 BFAR: 0x38383600 BF: 0x82 PC: 0x0806D62E at "_Balloc"  This error occurs randomly after multiple calls to snprintf(). Below is a simplified version of my actual code: #define BUF_SIZE 10 char temp_str[9][BUF_SIZE]; float temp[9]; for (int n = 0; n < 9; n++) { snprintf(temp_str[n], BUF_SIZE, "%.3g", temp[n]); } Fault Trace: task1() → snprintf() → _svfprintf_r() → _dtoa_r() → _Balloc() → <signal handler called>() → HardFault_Handler() at STM32f4xx_it.c Memory Layout (Snippet from Linker Script): /* Entry Point */ ENTRY(Reset_Handler) /* Highest address of the user mode stack */ _estack = 0x20020000; /* end of RAM */ _Min_Heap_Size = 0x200; /* required amount of heap */ _Min_Stack_Size = 0x400; /* requir

Hi,We are working on a board with the STM32H7S7Z8J6 in a BG144 package. We use cubemx to create the correct pinout for this part, but we see the datasheet has different pinout then the CubeMX tool. Is this a bug in CubeMX?   

I made a change to my project (using an STM32H7S3L8 part), saved the results, and a few days later tried to reload the project, but got a "Not a valid ioc file" error message.  Here is the output of the log file:```2025-02-17 10:59:38,352 [FATAL] ProjectFactory:568 - Exception caughtjava.lang.NumberFormatException: For input string: ""at java.lang.NumberFormatException.forInputString(NumberFormatException.java:67) ~[?:?]at java.lang.Long.parseLong(Long.java:719) ~[?:?]at java.lang.Long.valueOf(Long.java:1157) ~[?:?]at com.st.microxplorer.mcu.memorymap.MemInfoExtractor$ETHInfoExtractor.onETHEnable(MemInfoExtractor.java:4561) ~[STM32CubeMX:?]at com.st.microxplorer.mcu.memorymap.MemInfoExtractor.completInit(MemInfoExtractor.java:252) ~[STM32CubeMX:?]at com.st.microxplorer.mcu.memorymap.MemoryMapService.MMTActivated(MemoryMapService.java:1259) ~[STM32CubeMX:?]at com.st.microxplorer.mcu.memorymap.MemoryMapService.loadConfigV3(MemoryMapService.java:2578) ~[STM32CubeMX:?]at com.st.microx

Hello,(previous post was marked as spam - I don't know why, so I'm posting again...)I've been working on Provisioning my STM32H563 and after 3 weeks of not touching it, I am unable to perform Full Regression or Debug Authentication on my password-provisioned Nucleo Board. I tried using the generated bash scripts from CubeIDE/MX (which are using STM32_Programmer_CLI) and also STM32CubeProgrammer GUI.I remember before the vacation, I could open and close the Board at will. I always used the same password.bin.Provisioning always happened using the generated provisioning.sh script.Here is the Output of STM32CubeProgrammer (I found it has more info than dbg_auth.sh), after trying Discovery and Full Regression:  17:21:34 : Start Debug Authentication Sequence 17:21:34 : SDMOpen : 609 : open : SDM API v1.0 17:21:34 : SDMOpen : 610 : open : SDM Library version v1.1.0 17:21:34 : open_comms : 501 : open : Asserting target reset 17:21:34 : open_comms : 505 : open : Writing magic number 1

I'm using a NUCLEO STM32F303K8 board attempting to use FreeRTOS, and I have a halting problem when I use CMSIS V2. I found this out by just trying to toggle the built-in LED using HAL using one statically allocated task and observing that the LED only toggles once.(I have OSdelay of 500, so I should be able to observe it). When I run into the debugger, it gets stuck in the default_handler. I then tried using CMSIS V1 and it toggles just fine. My question is is there any documentation on this? I've tried looking around, but haven't had any luck.  I've used FreeRTOS on other STM32's/NUCLEO boards and I haven't had a problem using CMSIS V2. Just to clarify, I don't mind using CMSIS V1. I was just wondering if others knew the problem or experienced the same issue.

Hi,About rfalST25xVPollerFastReadMultipleBlocks and rfalNfcvPollerReadMultipleBlocks。I use st25r3916 to read NFCV tag.The farthest reading distance of my reader can reach 70mm.When I use the command RFALNFCVPoller Read Multipleblocks, I can successfully read data between 0-70mm, but when I use RFAL ST25XVPoller FastTreadmill Blocks, when the amount is between 55 mm and 70 mm, I will fail to read, and the returned error codes are mainly 04, 09 and 21. There is no problem with tag. I can read it with other competing products in this position. How can I determine what the problem is, the software configuration problem? Or is there not enough energy after the RF field is far away?Do you need any other configuration to use fast reading?I hope you can help me answer it. Thank you.

When using DMA to do a SPI transmit, I found a strange behavior. The problem is, that the communication to the DAC works for a few seconds, depending on the used frequency. After the few seconds only 1 byte instead of 3 bytes are sent and the NSS Pin (Hardware regulated) stays low. You can even see these two data items to transfer in S1NDTR (NDT). I used the approximately same code with Software NSS without any problem.I also get a DMA FIFO Error (FEIF) directly after starting the DMA stream, even when using DMA circular mode. Not every time but over 50% of the times when the communication is working I get the FEIF. When the communication is not working anymore, I do not get the FEIF anymore. I found these factors influencing the error:- Using DMA normal mode/ circular mode -> no difference- Enabling DMA FIFO -> no difference- Increase frequency of sending values to the DAC: communication breaks very fast- Decrease frequency of sending values to the DAC: communication does n

Hello,I'm using a STM32H743 and IS42S32160 SDRAM.  The SDRAM is in bank1, and I followed the instructions on how to setup the external memory from this guide:https://community.st.com/t5/stm32-mcus/how-to-set-up-the-fmc-peripheral-to-interface-with-the-sdram/ta-p/49457i can read/write the entire bank (64Mbytes) one word at a time, but then when I run a memory test, where it uses a pattern (incrementor) at each location the memory test fails.  Also, in debug mode, when I step through the program and watch the memory window, i noticed weird things happening.  Before this memory tests starts, the entire 64mb is initialized to x80000000 as shown below:Now the first write happens to location 0xc000_0000 <= 0000_0001, which seem to write there, but it also writes or reads  from addresses:  C000_0020, C000_0080, C000_00A0Something similar happens to the next memory locations:  .... etc... it does that through out the entire memory space.  I check

Given an MCU (say an STM32H755ZIT) and a function (say SPI2_MOSI), how can you find which pins may be configured as SPI2_MOSI, short of clicking on every pin in the Pinout View of the MX Device Configuration Tools?

I'm using the STM32H753ZIT6 NUCLEO Board. For some reason the User LED's are on by default even without any code on it. I tried to press the reset button but it would just blink the led's. I read on another forum to short the BOOT0 and Vdd pins but was hesitant to try that. The board works fine sometimes but it tends to give random/no outputs some times. 

Hi, I’m working with the IIS3DWB accelerometer to acquire single-axis data (Z-axis) using the following setup:Full Scale: ±16gSPI Mode 3 at 10 MHzTarget ODR: 26,667 HzI have attempted different methods to read the Z-axis data. First, I tried reading the Z-axis high (0x2D) and low (0x2C) registers using a timer with auto-increment. I also tried using 1AX_TO_3REGOUT mode and reading all 6 registers (0x28 to 0x2D) using a timer with auto-increment.I then configured the sensor with the following register settings:write_register(IIS3DWB_CTRL1_XL, 0x00); // Power Downwrite_register(IIS3DWB_CTRL6_C, 0x03); // Single Axis Mode (Z-Axis)write_register(IIS3DWB_CTRL1_XL, 0xA4); // Power On, Full Scale 16g, 26.667 kHz ODR write_register(IIS3DWB_CTRL3_C, 0x44); // BDU and Auto Increment Enabled write_register(IIS3DWB_CTRL8_XL, 0xF4); // High-pass and Low-pass Filterswrite_register(IIS3DWB_CTRL4_C, 0x01); // 6 Consecutive Single Axis Valueswrite_register(IIS3DWB_CTRL5_C, 0x20); // Wraparound Rounding

Since upgrading to 1.17.0 compile times have went from a pleasant time to wow, that is slow.  Anyone else experiencing this?Basic project from template: 22:45:47 **** Incremental Build of configuration Debug for project CompileTimeTest **** make -j4 all arm-none-eabi-size CompileTimeTest.elf text data bss dec hex filename 11996 9 1644 13649 3551 CompileTimeTest.elf Finished building: default.size.stdout 22:47:00 Build Finished. 0 errors, 0 warnings. (took 1m:13s.194ms) I've tried 32 cores to just 4 and the time difference is in a few seconds.  All build times are now in minutes when they used to be less than 20 seconds.

Hello,I would like to configure PA11 as an EXTI pin. I know that there exists the hardware limitation that there cannot exist two pins with the same pin number in different ports configured as an EXTI pin (I.E., I could not configure both PB11 and PA11 as EXTI inputs). PB11 is already configured as a UART RX pin. Will there be any conflict if I now attempt to configure PA11 as an EXTI input pin, I.E. a low bit being received by PB11 triggers the EXTI interrupt on pin 11? Or does this conflict only occur when two pins of the same number are both configured as EXTI inputs? 

Hi,I am using the STM32H7R7I8T6 in combination with the Macronix MX25L12833F on a custom board. As I understand it, I need to configure the External Memory Manager and the XSPI interface in STM32CubeMX and after initializing the flash via SFDP, the bootloader should jump into the application if the External Memory Loader is configured correctly. Am I right? It is not necessary to write a separate library for the flash and put it in memory mapped mode? When debugging the External Memory Manager, the error message EXTMEM_DRIVER_NOR_SFDP_ERROR_SFDP is returned at step “4 - Analyze SFPD structure to get driver information”.Does the External Memory Manager support all SFDP flash memory or is there something to consider? Also, I am wondering if the flash memory needs to support XIP (Execute in Place) in order for me to use the flash memory?

From my research, I've read that LwIP is written with FreeRTOS, but can be altered to support any OS. Since ST has made an effort to support/encourage LwIP and ThreadX, are there any resources/examples that we can reference?I am doing my evaluation with the STM32H753ZI and I want to utilize LwIP and ThreadX. I have played with the STCubeH7 LwIP examples on GitHub, but again, none are with ThreadX. If someone could also point me to a tutorial or documentation that explains the different components LwIP needs, that would also be helpful. As I've noticed some examples have different req files that the use needs to provide: ethernetif.h/c, app_ethernet.h/c, and net_conn.h/c, ethernet_perf.h, etc.

I am using the STEVAL-C34KAT2 with the STEVAL-STWINBX1 which is running the software FP-SNSDATALOG2 V3.0.0.Do I need to change anything in the FP-SNSDATALOG2 V3.0.0 software ?Or does the software automatically detect the STEVAL-C34KAT2 board ?Does anything need to be added to the device_config.json file ?I have read the user manual for the STEVAL-C34KAT2, it explains how to connect the board but there's no explanation on how to use it in terms of software.  Is it just plug and play or are there extra steps required ?  

Good day Folks,I am hoping you are able to shed some light on this odd XSPI clock behaviour.  I have connected XSPI2 to a W25Q64 Flash in QSPI mode.There are 'preamble' clocks present prior to the NCS being asserted. I've noticed that the number of preamble clocks depends on the frequency of the bus. The least I have seen is 150 clocks. As you can see below it's 641 clocks, prior to the NCS falling.I am guessing the clock is used internal by the XSPI peripheral, however the 'noise' on the bus certainly is undesirable.This prevents me from using a NCS other than the dedicated NCS pin. Other than that it looks like it creates additional delays in the XSPI transaction, with the reads maxing out about every 30us.This is with a XSPI read being done in a while(1) loop.The data is being correctly read when the NCS is low, expected Byte of 0x16:When the SCK preamble clocks are present I can see the data lines (e.g. IO0 below) go high impedance and rise to the external pullup, until t