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Among 20-odd PCBs populated with STM32G431CBUx controller, I am facing issue in programming one of them. All the others works fine, with no issues what so ever.The RDP is set to 0xFF, and the BOOT_LOCK bit was set. I searched through the community posts and tried the following methods.Set the BOOT0 pin High and enter through “Under Reset” mode → try to reprogram RDP to 0xAA. Try resetting through NRST and then reprogram the option bytes15:42:24 : ST-LINK SN : 0670FF56494889776713344115:42:24 : ST-LINK FW : V2J33M2515:42:24 : Board : NUCLEO-F303RE15:42:24 : Voltage : 3.25V15:42:25 : SWD freq : 4000 KHz15:42:25 : Connect mode: Under Reset15:42:25 : Reset mode : Hardware reset15:42:25 : Device ID : 0x46815:42:25 : Revision ID : Rev X15:42:25 : Debug in Low Power mode is not supported for this device.15:42:25 : UPLOADING OPTION BYTES DATA ...15:42:25 : Bank : 0x0015:42:25 : Address : 0x40022020 15:42:25 : Size : 84 Bytes15:42:25 : UPLOADING .

Hello everyone,While reviewing the STM32F302x6/x8 documents (DS9896 Rev 8 and RM0365 Rev 8), I found some inconsistencies in the memory map. Could you please look into them?DS9896 Rev 8, Table 19, page 49TIM1 is 0x4001 0800 - 0x4001 2FFF (10 K). It should be 0x4001 2C00 - 0x4001 2FFF (1 K). RM0365 shows TIM1 at 0x4001 2C00 - 0x4001 2FFF (1 K) and the range 0x4001 0800 - 0x4001 2BFF as reserved. It looks like the reserved area is inside the TIM1 row. The CMSIS device header also confirms the start address 0x4001 2C00: #define TIM1_BASE (APB2PERIPH_BASE + 0x00002C00UL) (file: stm32f302x8.h).DS9896 Rev 8, Table 19, page 50I2C3 0x4000 7800 - 0x4000 7BFF has size 9 K. It should be 1 K. RM0365 also says 1 K. Reserved 0x0804 0000 - 0x1FFF D7FF should start at 0x0801 0000. Main Flash is 64 K and ends at 0x0800 FFFF, and RM0365 shows 0x0801 0000 - 0x1FFF D7FF. Typo: 0x2000 4000 - 3FFF FFFF should be 0x2000 4000 - 0x3FFF FFFF.DS9896 Rev 8, Table 19, page 51 Reserved 0x0004 0000 - 0x07FF FFFF sho

Help, how do I perform flashing only without debugging when using STM32CubeIDE for VS Code? I have reviewed previous posts, but the most recent Q&A on this issue seems to be from a year ago, and the methods mentioned there appear to be outdated. I am not sure how to achieve this functionality in the latest version.

Hi, I’m beginner in this and where’s no a lot of manuals how to do that ,but looks like I’m done everything but still experience some ”hangs” like after run every debug or run I can’t to anything it’s halt and that’s all Would be if somebody will help me with that because it’s makes me crazy , THANKS A LOT to this strange which is spent his/her time to help me) here’s my mcuhttps://www.aliexpress.com/item/1005010547748358.htmlhere’s the log what I get when I try to debug nor run , and I tried different ways to launch it but still I experience “halts” of mcu and strange issues with stm32 programmer (looks like it doesn’t see the mcu screenshot below )    STMicroelectronics ST-LINK GDB server. Version 7.13.0Copyright (c) 2026, STMicroelectronics. All rights reserved. Starting server with the following options:Persistent Mode : DisabledLogging Level : 1Listen Port Number : 61234Status Refresh Delay : 15sVerbose Mode : DisabledSWD Debug : EnabledInitWhile : Enabled Waiting for debugger con

Hello everyone, I would like to ask if it is possible (and if so, how) to make both m4 and m7 get an interrupt made by the user button in in the nucleo board, since the only Pin Context Assignment options on CubeMX is either m4 or m7. Do I have to do it "manually" by writing the code to register the interrupt on the other mcu? Thanks in advance!

hi,In STM32G070C, it seems there is no remap mechanism to select wich pin(PC5,or PC11) should be used for USART3_RX.if i configure PC5 and PC11 are USART3_RX all at once, simultaneously, what will happen?Best regards  

CubeMX Version 6.18.1 (tested with STM32G491VET6) shows no "Clear Input" parameter group for TIM16/TIM17, so the OCREF-clear feature cannot be configured from the tool.The hardware does support it, per RM0440 Rev 9:§31.4.17 "Clearing the tim_ocxref signal on an external event" (TIM15/16/17 chapter) TIMx_CCMR1 bit 7 OC1CE, x = 16..17 (p. 1490) TIMx_AF2 OCRSEL[2:0], x = 16..17 (p. 1505) selecting tim_ocref_clr0..7 Table 76 "Interconnect 3": TIM16/17 ocref_clr sources include the COMP1..COMP7 outputsUse case: cycle-by-cycle peak-current limiting of a synchronous buck (COMPx clears OC1REF; CH1N provides sync-FET freewheel). For comparison, TIM1/TIM2 panes do offer "Use ETR as Clearing Source" / "Clear Input Source".Currently the only workaround is manual register writes in USER CODE (TIMx->AF2 OCRSEL + TIMx->CCMR1 OC1CE), which the .ioc cannot capture.Request: add the Clear Input group (OC1CE + OCRSEL source selection) to the TIM16/TIM17 panes for STM32G4. Image 1: Outline of RM0440

 NUCLEO-H753ZI Board Recovery Case Description: STMicroelectronics ST-LINK GDB server. Version 7.11.0Copyright (c) 2025, STMicroelectronics. All rights reserved. Starting server with the following options:Persistent Mode : DisabledLogging Level : 1Listen Port Number : 61234Status Refresh Delay : 15sVerbose Mode : DisabledSWD Debug : EnabledInitWhile : Enabled Target no device found Error in initializing ST-LINK device.Reason: No device found on target.  Board: NUCLEO-H753ZIBoard part number: MB1364-H753ZI-E01MCU: STM32H753ZIT6 / STM32H753ZIAffected quantity: 3 boards  I have three NUCLEO-H753ZI boards, model MB1364-H753ZI-E01, with the same hardware issue. On all three boards, U2 (5V ST-LINK protection IC) becomes significantly hot when the board is powered through the USB connector, and LD6 (ST-LINK USB overcurrent indicator) blinks red. "Error in initializing ST-LINK device."I checked the board and found that 5V is present at the input of U2, but the output toward the ST-LINK section

Hello everyone,I'm developing an application using the STM32H563 with TrustZone enabled. Online tutorials first show configuring the fuse bits using the STMCubeProgrammer software:TZENSECWM1_STRTSECWM1_ENDSECWM2_STRTSECWM2_ENDThen, the application is installed in the STMCubeIDE, where it is saved and executed correctly.However, if the developer tries to install the application without going through the first step, the code is unable to exit the safe zone, resulting in a hard fault error. This is because the IDE, when TrustZone is enabled, assumes that all FLASH memory is in the safe zone.I would like to change these fuse bits without using STMCubeProgrammer. I believe it's possible, but I haven't found any information where the result is satisfactory. Could someone help me?

Hi all, I’m searching a method to configure the NVRAM STPMIC25 VINOK_rise param in the 0x90 adress Register (NVM_MAIN_CTRL_ SHR1) As this is a sensitive reg I’m supposing this field and may others are Locked in the NRAM in the DK board from ST. Please I’m considering running Board with 3.3V power Buck Converters. Cheers, Habib 

Hello STM32 Community,I am currently working on a USB Flash Drive interface using STM32G0B1RET6 with USB Host and FatFs.The USB Flash Drive is working correctly. When I plug in a USB Pendrive, my STM32 can detect it, mount the filesystem, and successfully create/write files to the Pendrive.Now I would like to display/check the following information:Total USB Flash Drive storage Used storage Free/available storage Detect whether the USB is almost fullMy current code is:static void USBH_UserProcess(USBH_HandleTypeDef *phost, uint8_t id){ switch (id) { case HOST_USER_CLASS_ACTIVE: Appli_state = APPLICATION_READY; USB_Detect_flag = 1; // USB is plugged Mount_USB(); HAL_GPIO_WritePin(GPIOC, LED_RED_Pin, GPIO_PIN_RESET); /* Check USB free space */ if (usb_space_result == FR_OK) { displayText16x16_DMA(20, 190, "USB HAS SPACE",

Hi,I am using the following codes to do system clock initialization on my STM32F411E-Discovery board:  /** Initializes the RCC Oscillators according to the specified parameters * in the RCC_OscInitTypeDef structure. */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; RCC_OscInitStruct.HSEState = RCC_HSE_ON; //Use X2 Crystal RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; RCC_OscInitStruct.PLL.PLLM = 4; RCC_OscInitStruct.PLL.PLLN = 192; RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4; RCC_OscInitStruct.PLL.PLLQ = 8; if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) But  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)returns time out error.I am sure crystal X2 is connected, but I don’t understand why it gives me time our error. Previosuly I also tried:RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS;that also threw time out error, I gave up this configuration because I am not sure if SB14 and SB16 are bridged

We have a project which uses STM32CubeIDE (Eclipsed-based). It has a Makefile which we use to compile the code and upload the code to the target. Since I know ST has made a new STM32CubeIDE VSCode extension, I wanted to have a trial to see if I can convert the existing Eclipsed based project to VSCode based project. I installed the STM32CubeIDE extension in VSCode and other necessary components. I followed the migration guide to generate a CMake project using STM32CubeMX. However, it never worked since the new CMake file doesn’t take what the original Makefile does in my project. It missed a lot of compiler and scripting options. After the migration, the build process failed and never succeeds. Since Makefile works great in the original project (either in CLI/GUI mode), why does the migration require user to convert it to CMake? Many Unix/Linux users prefer Make instead of cmake. It gives you better control over the source code. I would suggest ST that if you really want to make a VSCo

Hello everyone,I'm trying to develop an application with LwIP without an operating system using the STM32C5A3x.When I set the LwIP operating system to “No OS,” I see some files in the CMake project that call FreeRTOSConfig.h, and the compilation fails.  Is anyone else experiencing the same problem? I’d also like to ask if there’s any information about the release of a new version of STM32CubeMX2.Thanks for help.

TouchGFX Designer 4.26.0 Given the following “empty” SVG file:<?xml version="1.0" encoding="UTF-8" standalone="no"?><!-- Created with Inkscape (http://www.inkscape.org/) --><svg width="1024" height="600" viewBox="0 0 1024 600" version="1.1" id="svg1" xml:space="preserve" xmlns="http://www.w3.org/2000/svg" xmlns:svg="http://www.w3.org/2000/svg" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:cc="http://creativecommons.org/ns#" xmlns:dc="http://purl.org/dc/elements/1.1/"> <rect x="0" y="0" width="1024" height="600" fill="none"/></svg>I can select it as SVG file in Designer:But sources do not get generated for the file. So when I try to build the simulator Build in Visual Studio I get the following error: 

Subject: X-CUBE-CLASSB-L4 (STL) — Fault Injection Method for Flash/CPU/RAM Self-Tests on STM32L451CETI am applying X-CUBE-CLASSB-L4 (Self-Test Library, STL) on an STM32L451CET MCU to implement CPU/Flash/RAM self-tests for IEC 60730-1 Class B certification.Main issue: No matter what method I try, the Flash test never passes (always reports a failure / never completes successfully under normal conditions).Certification requirement: Our certification body requires us to demonstrate both the normal (pass) case and the fault (failure) case for each test, specifically by actually altering real values during test execution:CPU test: by actually changing register values during the test Flash test: by changing the CRC value, or modifying Flash memory contents while the test is running RAM test: by modifying RAM contents while the test is runningI understand that ST's recommended method is to use STL_ArtifFailingConfig to perform fault injection. However, this only simulates a failing configurat

Hi,I'm working with an STM32N6570-DK and need the microSD slot (CN13, SDMMC2) to run at 1.8V signaling instead of the 3.3V default. The device I'm connecting only supports 1.8V, and the target speed is modest, around 25 MHz.What's the correct procedure to make this switch on this board?So far I've driven SD_SEL (PO5) high to flip U32, but CN13 pin 3 still measures 3.3V. AN5967 (Getting started with hardware development for STM32N6) section 12.4 points to PWR_SVMCR2.VDDIO5VRSEL together with OTP124 bit 13 (HSLV_VDDIO5), which currently reads 0 on my board.Two things I'm unsure about: Is burning HSLV_VDDIO5 actually required for 1.8V operation, or only to reach the datasheet frequencies?  Does burning it permanently prevent the slot from working with ordinary 3.3V SD cards?  

STM32CubeMX2 Unable to Add CMSIS-DSP Properly? Manual Integration Using CMake and Project Structure OptimizationI. Background of the IssueI recently used the STM32C542RCT6 development board to conduct trigonometric function performance tests. The development environment is as follows:Project     Version or Configuration MCU STM32C542RCT6 Development Environment VS Code Project Generation Tool  STM32CubeMX2 1.1.1 Build System CMake CMSIS 6.3.0 CMSIS-DSP 1.17.1 Toolchain     GCC The goal of this test is to compare the computational performance of the STM32C5 hardware CORDIC, CMSIS-DSP, and the standard math library’s `sinf()` function.The CMSIS and CMSIS-DSP packages were installed in the CubeMX2 Pack Manager, but a problem arose when generating the project: while the CMSIS Core integrated successfully, the CMSIS-DSP was not generated in the project directory as expected.Even after manually modifying the .ioc2 project configuration to include the CMSIS-DSP compone

JW

Background: I am trying to bring up simultaneous operation of both FDCAN peripherals on an STM32G0, but due to a combination of unfamiliarity with the clock internals, and a misleading baud rate calculator, I spent a while trying to debug what I thought was a non-functioning FDCAN2 peripheral, but was actually working at an unexpected frequency.   FDCAN1 configuration: FDCAN2 configuration (noting that the prescaler is 8, while the clock divider is 1): with this configuration, FDCAN2 transmission works as expected (verified using a PEAK CAN dongle) at 250kbaud when I am running it on its own in normal operation -- started the FDCAN2 peripheral using HAL_FDCAN_Start(&hfdcan2). However, if I also start FDCAN1, then I can no longer read any transmissions from my CAN dongle. After unsuccessfully attempting to debug the issue in firmware, probing my CAN lines revealed that FDCAN2 was operating at 30kbuad (250k/8 = 30k). Going back at the CubeMX configuration, I tried changin

We're bringing up an ST87M01 module on a custom board and have not yet achieved a successful first AT command response. We've implemented what we believe is the correct wake/power sequence based on your EC-Lib reference source and a third-party open-source host library, but want to confirm we're not missing an ST87M01-specific requirement before we keep debugging on our end. What we've implementedVBAT_DCDC_EN, NRESET (active low), WAKE_UP (active low) and RING are driven via a host-side I2C GPIO expander, not directly from MCU pins. Power-up sequence: assert NRESET high (out of reset), hold WAKE_UP idle-high, wait ~3 s settle, then pulse WAKE_UP low for ~100 ms and release it high. Separately, we also send a single \r byte over UART before each AT command (per the wake behavior we observed in ST87EC_Wrapper_WakeUp() in your EC-Lib reference), followed by a short settle delay before sending the actual command.We're currently sending both the GPIO WAKE_UP pulse and the UART \r wake, sinc

void HAL_MRSubG_IRQ_Callback(void) { uint32_t irq = __HAL_MRSUBG_GET_RFSEQ_IRQ_STATUS(); if (irq & MR_SUBG_GLOB_STATUS_RFSEQ_IRQ_STATUS_RX_OK_F) { last_rx = HAL_GetTick(); HAL_GPIO_WritePin(LD1_GPIO_Port, LD1_Pin, GPIO_PIN_SET); if (HAL_MRSubG_GetBytesOfTransaction() <= ring_buffer_u8_free(&radio_ring_buffer) && radio_packet_fifo_free(&radio_packet_fifo) != 0) { for (uint8_t i = 0; i < HAL_MRSubG_GetBytesOfTransaction(); i++) { ring_buffer_u8_write(&radio_ring_buffer, radio_rx_buf[i]); } radio_packet_t radio_packet = { .len = HAL_MRSubG_GetBytesOfTransaction(), }; radio_packet_fifo_write(&radio_packet_fifo, radio_packet); } __HAL_MRSUBG_STROBE_CMD(CMD_RX); __HAL_MRSUBG_CLEAR_RFSEQ_IRQ_FLAG( MR_SUBG_GLOB_STATUS_RFSEQ_IRQ_STATUS_RX_OK_F); } if (irq & MR_SUBG_GLOB_STATUS_RFSEQ_IRQ_STATUS_RX_TIMEOUT_F) { __HAL_MRSUBG_STROBE_CMD(CMD_RX); __HAL_MRSUBG_CLEAR_RFSEQ_IRQ_FLAG( MR_SUBG_GLOB_STATUS_RFSEQ_IRQ_STATUS_RX_TIMEOUT_F); } if

HelloUsing NTAG5 Link (NTP53121G0JTZ) in SRAM Mirror mode with an STM32G0B1RE I2C master at 100 kHz. WDT is disabled (WDT_EN=0, WDT_CONFIG=0xFFFF).Problem: A single I2C multi-block write to SRAM (64 blocks, 256 B starting at 0x0000) NACKs after the tag accepts exactly one 4-byte block.Questions: Are multi-block SRAM writes supported in SRAM Mirror mode, or only in SRAM Pass-Through mode (AN12364)? If supported in mirror mode, what configuration am I missing?

Hi,The CRA is making Secure Boot and Secure Update increasingly important for a wide range of products.I have fully reviewed the playlist at https://www.youtube.com/playlist?list=PLnMKNibPkDnGd7J7fV7tr-4xIBwkNfD-- as well as documents UM2262 and AN5056.Unfortunately, AN5056 is far too brief to properly understand how to implement this yourself.The video series only features controllers that are already covered in the existing examples.I wanted to ask if it might make sense to continue the video series and address these specific points. I believe this would be a huge help to many customers.Right now, I feel like it will take me months to customize SBSFU for my needs.Both the video series and AN5056 lack coverage of fundamental aspects, such as:-Changing the update interface from UART to something else—for example, USB (virtual COM) or CAN. Where exactly are the lines of code that need changing?-Implementing and explaining a controller that isn't currently covered by an example (e.g., ST

We are currently working on flashing an STM32L071KZ MCU using the STM32 bootloader.The flashing process completes successfully when using a 64-byte payload. However, when we reduce the payload size to 8, 16, or 32 bytes, we observe unexpected behavior. In each case, only the first 8, 16, or 32 bytes of every 64-byte flash block are programmed successfully, while the remaining writes within the same 64-byte block do not take effect. This pattern repeats consistently for every subsequent 64-byte-aligned address.We have verified that:The correct data is being transmitted to the MCU. The target flash address is incremented correctly for each write operation. The bootloader acknowledges the write commands.Despite this, the flash programming behaves correctly only when using a 64-byte payload.Is there any known limitation or programming requirement for the STM32L071KZ bootloader or flash controller regarding payload sizes? Are there any additional steps or constraints that must be followed w