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Hello, I am working with X-NUCLEO-WB05KN1 together with NUCLEO-U083RC. I had previously tested U0 consumption in Stop mode and I got around 1.5uA (using 3.3V supply and LSI). From the datasheet it says that STM32WB05KZ should be an ultra low-power MCU, however I am using the Beacon app from the X-CUBE-WB05N software package and I am getting measurements of around 37mA. Is this related with the SPI firmware (DTM binary) flashed into the shield to run the example? I would like to achieve a consumption on the uA scale, do I need to make my own firmware to the chip? If so, is there any example and how to communicate with my U0?I am supplying 3.3V into the CN6 pin 4 and measuring with a multimeter so the ST-LINK is now being powered.BR 

Hello,We are currently working on STM32C542CCT6 from the STM32C5 series and developing custom Flash and Data Flash drivers.Issue 1 – Hard Fault when accessing FLASH_SIZEWhile executing code generated by STM32Cube, the following check causes the system to enter the Hard Fault handler:if (FLASH_ADDR < (FLASH_BASE + FLASH_SIZE)) /* Main User Flash */The FLASH_SIZE macro reads the value from the device information area. However, when the code attempts to access FLASH_SIZE, the system immediately enters the Hard Fault handler.If we manually hardcode the flash size value, the code works correctly.Our questions are:Is there any specific register configuration or initialization required before accessing FLASH_SIZE on this device?Is this region restricted due to Trust Zone or privileged access on STM32C5 devices?Issue 2 – NMI when reading Data FlashWe have enabled Data Flash by setting: EDATA_EN = 1We are trying to read from the Data Flash base address:0x09000000using a pointer-bas

I’m making AOI program for STSAFA110DFSPL02 and would like the correct top marking because I couldn’t find it in the datasheet.The received part has SF3C B317 marked in the top side and need to confirm that is correct or not.

Hi everyone, We are encountering a XSPI Deadlock on our STM32H7S7-Discovery board (STM32H7S78-DK).To provide some context, our system is configured as follows: External FLASH: Connected to XSPI1. Swapped through XSPIM to port 2 and operates in memory mapped mode. MCE1 is activated across the entire address range using the AES-STREAM Cipher. External PSRAM: Connected to XSPI2. Swapped through XSPIM to port 1 and operates in memory mapped mode. MCE2 is activated across the entire address range using the NOEKEON-BLOCK Cipher. The issue occurs when running an LZO decompression algorithm. The algorithm reads compressed data from the PSRAM and writes the decompressed output back to the PSRAM, while the code is being executed on External FLASH. At some point during decompression, the core completely freezes, no HardFault or BusFault is triggered, and the debugger permanently loses its connection to the core. We have tried multiple approaches to resolve, including the offic

HiI saw the pad dimensions for the SGT070R70HTO listed in the datasheet.But I don't know the dimensions of the parts I marked in red. So I want you to tell me that. Thank you.

Hello,We are assessing security maintenance for an STM32MP1 product using linux-stm32mp. Could ST clarify the following? Is the maintenance policy in the 2021 "FAQ: Updating OpenSTLinux" (https://community.st.com/stm32-mpus-61/faq-updating-openstlinux-19) still current? How are security fixes delivered after a release: through component branches, tagged minor releases, or another mechanism? Has ST published updated guidance in preparation for the EU Cyber Resilience Act? Does ST assess kernel.org CNA CVEs against its vX.Y-stm32mp branches? Are per-CVE affected/fixed decisions published anywhere, such as a vulnerability list, VEX document, or CVE_STATUS entries in meta-st-stm32mp? For security vulnerabilities in ST-specific kernel changes that have not been upstreamed, what is the CVE assignment and advisory process? Where are fixes announced? The FAQ describes 1.5 years of feature development, 2.5 years of corrections, and a possible additional year of vulnerability-related relea

Setup: STM32H757 (device ID 0x450, rev V), ST-LINK/V2 firmware V2J48S7 over SWD, STM32CubeProgrammer v2.23.0 CLI on Windows 11.Problem 1: the CM4 boot address can't be set.STM32_Programmer_CLI -c port=SWD mode=UR -ob BOOT_CM4_ADD0=0x080E BOOT_CM4_ADD1=0x080Eprints "Warning: Option Byte: boot_cm4_add0, does not exist" (and the same for add1), and exits with code 0, so scripts don't notice. "-ob displ" shows only the single-core BOOT_ADD0/BOOT_ADD1, with no BCM4/BCM7. The silicon is dual-core: FLASH_BOOT4_CUR (0x52002048) reads correctly, and BCM4/BCM7 are set in FLASH_OPTSR_CUR.Cause, as far as I can tell: in Data_Base/STM32_Prog_DB_0x450.xml the H757 matches configuration 0 ("Security extension available && multi-core"). In v2.23.0, every dual-core field leaves out config 0, while the single-core BOOT_ADD0/1 does include it:BCM4 (FOPTSR_CUR): config "1"BCM7 (FOPTSR_CUR): config "1,4,5"BCM4, BCM7 (FOPTSR_PRG): config "1,4,5"BOOT_CM4_ADD0/1 (FBOOT4_CUR and _PRG): config "1,4,5"BO

I’ve configured dual channel simultaneous with overrun overwritten and DMA. I’ve connected ECN 1313 incremental signals directly to MCU differential adc. 10ksps, 64.5 ADC sample time, 50MHz ADC clock. The noise on 12bit sampling is more than expected comparing to 10bit. Or in other word noise in 10bit is less than expected compared to 12 14 16!!!12 bit capture10bit data capture, as you can see in 12 bit capture red and green dots suggest there should be at least 8 code levelIt seems I have more noise than expected in 12 bit data capture, doesn’t it? Also I have attached .ioc. and there the only parameter i am changing manually is the bit depth in main.c manually is “hadc1.Init.Resolution =”.And here is my statistic calculation:statisticsI think there is something wrong with the hardware! Because 12 bit reading is consistent with 14 and 16 bit depth. It means hardware have more noise on sampling 12 14 16 bit and it seems odd! I havev also checked errata and there was only told if you ha

Subject: STM32MP257F-EV1 (MB1936D) not booting after PA6/PA7 MDF1 rework + SAI2 speaker addition — no console output, no USB DFU enumerationBoard: STM32MP257F-EV1, board reference MB1936DBackground — MDF1 microphone rework:We were bringing up PDM microphone capture on MDF1 (channel 6, PA6=SDI6, PA7=CCK0). On this board revision, PA6/PA7 are hardwired only to the onboard RTL8211F Ethernet PHY (ETH3.TXD0/TXD1 via series resistors R169/R175) with no external header access. To route these pins to MDF1 instead, we physically soldered a wire tap onto R169 and R175, and disabled Ethernet in our device tree so MDF1 could claim PA6/PA7 without a pinmux conflict.Background — speaker interface addition (same device tree, added afterward):Separately, we added a playback path using a MAX98357A I2S digital audio amplifier driving a 4Ω/5W speaker, over SAI2A:- CN5 pin 12 (PJ11, SAI2_SCKA) -> MAX98357A BCLK- CN5 pin 35 (PJ3, SAI2_FSA) -> MAX98357A LRCLK- CN5 pin 38 (PJ12, SAI2_SDA) -> MAX9835

Wiring from st link to the stm32g061Error message It does not connect to STM32CubeProgrammer with the stm32G061 it keeps saying Error: unable to get core IDError: No STM32 target found! If your product embeds Debug Authentication, please perform a discovery using Debug Authentication. I have NRST pulled high with a 10k ohm resistor and then a tactile button which will make it go low when pressed.  The pinout for the STM32G061 is the same as the STM32G050 and when I have the same wiring as I did with the STM32G050 on this st link v2, but with the stm32G050 it connected correctly in STM32CubeProgrammer.  Why doesn’t it work with the STM32G061?

I previously wrote the code for my project and generated the HEX file. I copied my project folder from the workspace_2.1.0 directory to a USB flash drive.Now, when I open this copied project on a new PC using STM32CubeIDE, I cannot find the page where the settings for generating the HEX file are configured.Could someone please help me?  

Hello,I am facing some issues with NetXDuo, where i see traffic on the RGMII RX lines, but RX DMA does not process any frames / no interrupts fire. I have the following setup:I am using a custom board based on the STM32N657 with an ADIN1300 Gigabit Ethernet PHY connected over RGMII.Software stack:STM32Cube FW_N6 V1.3.0 ThreadX NetXDuo Static IPv4 configuration Secure only application Caches disabledThe PHY is configured over MDIO and link comes up successfully. The resolved PHY speed matches with what is seen on the host side and with the MAC speed configuration.What is working:The PHY side appears to be working correctly. For example, when forcing 10Mbps, i can clearly probe the RGMII lines and see:RX_CLK present RX_CTL activiy for each incoming ARP/ping RXD0..3 activity during the frameThis confirms that Ethernet frames are being received by the PHY and forwarded onto the RGMII interface toward the MCU.The following have also been checked/tried:RGMII pin mux tried disabling broadcast

Hi!I think a have found a bug in CubeMX for STM32MP257F processor.If you go to RIF - RISAB - VDERAM. You will find that the region size can only be 0x21000. That's more than 128 kB, according to the data sheet.SYSRAM1, SYSRAM2, SRAM1, SRAM2, RETRAM have 0x20000 as maximum region size.Question: If this is a bug, then I want to send a PR to the Github ST repository of the MP2 firmware. Can you guide me where the code is so I can make a PR?

in “usbd_msc_scsi.c” at function “SCSI_ModeSense6”/* Check If media is write-protected */  if (((USBD_StorageTypeDef *)pdev->pUserData[pdev->classId])->IsWriteProtected(lun) != 0)  {    MSC_Mode_Sense6_data[2] |= (0x1U << 7); /* Set the WP (write protection) bit */  }  else  {    MSC_Mode_Sense10_data[2] &= ~(0x1U << 7); /* Clear the WP (write protection) bit */  }is writing to the wrong place !!!   Change it to:MSC_Mode_Sense6_data[2] &= ~(0x1U << 7); /* Clear the WP (write protection) bit */Note:The wrong write mainly cause the write protection to stay on if its once set and never be able to unset without reseting the scsi device.Took me days to track down this bug !! best regards,Labmaster 

HiI am trying to program STM32U535 series IC via CLI method. It will be good enough to know and understand any return code for STM32 programmer. I have checked on forum and understood, this was not available for long time.Is CLI return codes are available for STM32Programmer?

We need to develop the offline tool to program the device ST72UD05, it is seems similar with L9805E.But we could not find the definition of the programming interface or the programming protocal.It contain the EPROM/OTP, it is very different with other ST72 family devices which programmed with ICC.So we need the programming document about programming the device.

Dear all,I am facing some compiling issue on STM32CUBEIDE 2.2.0 with STM32G071KBI was trying to use st25r3916B NFC library and i have added ST/RFAL/Include & sources and relevant middleware into path & symbol of project.However during build,../Debug/../Core/Src/stm32g0xx_it.c:161:(.text.EXTI4_15_IRQHandler+0x14): undefined reference to `st25r3916Isr'C:/ST/STM32CubeIDE_1.16.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/bin/ld.exe: (st25r3916Isr): Unknown destination type (ARM/Thumb) in ./Core/Src/stm32g0xx_it.o../Debug/../Core/Src/stm32g0xx_it.c:161:(.text.EXTI4_15_IRQHandler+0x14): dangerous relocation: unsupported relocationcollect2.exe: error: ld returned 1 exit statusmake: *** [makefile:64: MCU_STM32G071KBU6.elf] Error 1 Need advice please! Thanks.My code is reference from the ST25NFC_Embedded_Lib_ST25R3916(B)_1.8.0 and the reference co

Environment - Device: STM32H562ZI- Reference manual: RM0481 Rev 5- HAL: STM32Cube H5 HAL Driver V1.5.0- Peripherals: GPDMA used for SPI slave Tx/Rx. SPI in slave mode, normal (non-circular) transfers, no linked-list. Summary On our SPI slave DMA path, the DMA channel becomes permanently stuck after an SPI error, and SPI communication never recovers until the device is power-cycled. The cause is that `GPDMA_CxCR.SUSP` gets written to a channel that has **already completed its transfer and stopped** (EN=0, IDLEF=1). In that state `GPDMA_CxSR.SUSPF` is never set, so `GPDMA_CxCR.RESET` is never written and **SUSP stays set**. Setting `EN=1` afterwards suspends the channel immediately after start, and the driver can no longer escape that state. Observed register sequence (Tx channel, real measurements) ```1) Block transfer completes. Hardware clears EN.CxCR = 0x00805D00 (EN=0, SUSP=0, SUSPIE=0)CxSR = 0x00000001 (IDLEF=1) 2) An SPI error occurs right after this point.SPI ErrorCode = 0x84 (UD

The installer denies installation in the existing directory. But it also does not offer an option to abort. So you can kill ithe installer only from the starting console or rom windows frame allows. An abort option in the installer would be fine. And maybe an option to refresh an existing version that was perhaps screwed up somehow. Moved from: MX2 rant: Installation starts with bad size to display Continue button and is not resizeable 

Hello everyone. Hi everyone.Please forgive any inaccuracies in this post—it’s my first one.For my new project, I used the STM32C552KET6 microcontroller.The chip is mounted on a custom PCB I designed.One of the board's functions is to communicate with a PC via a virtual COM port (over USB).I’ve successfully used this type of communication in other projects before on G4, L4 microcotrolers, but this time I can't get it working and have no idea where I might be making a mistake.The electrical connections are definitely correct; I can connect to the microcontroller using STM32CubeProgrammer and read/write to Flash memory via USB.I used the STM32CubeMX2 tool (version 1.1.1) for configuration.The clock configuration is default, and the USB clock frequency is 48 MHz.In the Connectivity section, I selected: USB_DRD_FS – DEVICE (device mode); all advanced features are disabled; the USB_DP and USB_DM pins are assigned to PA12 and PA11, respectively.Global interrupts and IRQ handling are enabled.I

Tool: ST Edge AI Core v4.0.1-20581 (7ed50de05), target stm32n6Neural-ART compiler: 1.1.3-275Runtime: ST Neural ART (LL_ATON api) v1.1.3, atonn-v1.1.3-275-g6770925dBoard: STM32N6570-DK, device 0x486, Cortex-M55Host: Windows 11, STM32CubeProgrammer 2.23.0, gnu-tools-for-stm32 14.3.1WHAT HAPPENSA 23x60 -> 30x5 INT8 TCN, generated for stm32n6 with the Neural-ART compilerand run on the NPU, returns an output that is not the INT8 graph's.This is not an application bug. "stedgeai validate --mode target", run againstyour own NPU_Validation project with your own random stimulus, reports theboard's output as essentially uncorrelated with the reference model thenetwork was generated from:  acc=n.a. rmse=2.543027878 mae=1.976331592 l2r=1.100639820  mean=-0.346161 std=2.520198 snr=-5.872663 nse=-2.889206 cos=0.091053cos 0.091 is no correlation. snr -5.87 dB is noise above signal. nse -2.889 isworse than answering with the mean of the reference. l2r 1.10 is an errorlarger than the quantity it is

Hardware used:STM32L152 Custom board I've been using a STM32U585 Discovery kit for a few days and have succesfully run several programs on it. However today I suddenly got this error in STM32CubeIDE when trying to run a new program:---------------------------------------------------------------------------------------------------------------Error: Data mismatch found at address 0x0800899C (byte = 0x31 instead of 0x33)Error: Download verification failed---------------------------------------------------------------------------------------------------------------Trying to upload different programs gave the same result, but with the mismatch at different addresses.First time the code programmed successfully in the memory. After whenever I tried to program it using stmcube ide or stmcube programmer, it gives the verification failed error in the stmcube programmer and failed to erase memory in stmcube ide. I have no option bytes enabled. I can erase the memory using stmcube programmer but s

Hello,I am debugging SPI3 communication between two STM32H755 boards: UC1 = SPI master UC2 = SPI slave SPI3, full-duplex DMA used for TX/RX FreeRTOS STM32H755 The problem is that the first SPI transaction can be completed correctly, but the following transaction does not behave as expected.Before starting the SPI data exchange, I also perform a handshake/synchronization sequence between the two boards to ensure that both sides are ready. The handshake itself is implemented before the SPI test, but adding this synchronization does not resolve the issue.The intended sequence is:UC1 (Master) UC2 (Slave)SYNC ----------------> receive SYNC <---------------- OKPING ----------------> receive PING <---------------- PONGPING ----------------> receive PING <---------------- PONGIn the actual test, the first exchange can be received correctly, but the slave does not continue responding correctly on

 Hi ST team,I am using the ST VD66GY image sensor connected to a Rockchip RV1106 processor with the Rockchip hardware ISP.I have successfully enabled the camera pipeline and can capture images, but the image quality has a strong greenish color cast and the colors look desaturated, even under a bright indoor room with white LED lighting.Current setup Sensor: ST VD66GY Processor: Rockchip RV1106 ISP: Rockchip RKISP (hardware ISP) Capture: RAW from VD66GY → RKISP → Image output Observed issue Strong green tint across the entire image Skin tones appear gray/green Low color saturation Indoor lighting is much brighter than what the captured image suggests I have attached three sample images captured with the current ISP settings.Questions Does ST provide an IQ tuning file or reference tuning parameters for VD66GY when used with a third-party ISP such as Rockchip RKISP? Are there recommended AWB calibration, Color Correction Matrix (CCM), or Lens Shading Correction (LSC) values