Posted on May 17, 2011 at 13:25According to the revision history of the STM32 Reference Manual (RM0008), the RAM size register paragraph was removed in revision 6 (September 2008). There is no explanation as the change description says: Quote:“RAM...
Posted on May 17, 2011 at 13:05Quote:Your analysis of Figure 7 is different from mine... The diagram says ''If (APB1 prescaler = 1) x1 else x2''. Or is my copy wrong?That was my mistake. Your interpretation of the figure is correct. What I should ha...
Posted on May 17, 2011 at 13:05According to figure 7 on page 68 of the STM32 reference manual (http://www.st.com/stonline/products/literature/rm/13902.pdf), the APB1 clock is multiplied by 2 before it is fed to the timers but only when the APB1 pres...
Posted on May 17, 2011 at 13:03Quote:And this is timer capture and read: Code: TIM_GenerateEvent(TIM2, TIM_EventSource_CC1); uSeconds = TIM_GetCapture1(TIM2) | (TIM_GetCapture1(TIM3) << 16) | (TIM_GetCapture1(TIM4) << 32) | (TIM_GetCaptur...
Posted on May 17, 2011 at 12:58Here are some of my STM32 wishes: 1. Fewer flash wait states at high operating frequencies 2. True 32-bit peripherals with word, halfword, and byte access. In particular, this means that 32-bit registers (such as the s...
