Posted on October 16, 2014 at 11:30 .ExternalClass11B1744985E14676887C8F042F0B5239 p {margin-bottom:0.1in;line-height:120%;} Hi,I am writing a host stack and I have noticed various issues with the documentation and the hardware.Issue #1The pdf in...
Posted on October 16, 2014 at 11:30 .ExternalClassE693089A00C04AC1B8142AED96FA644F p {margin-bottom:0.1in;line-height:120%;} Hi,I am writing a host stack and I have noticed various issues with the documentation and the hardware.Issue #1The pdf in...
Posted on August 30, 2016 at 09:42About Issue #5 The NAK processing in slave mode (without DMA). In OUT direction the documentation suggests (as well as some libraries) that multiple packets can be queued. However this creates several implications. ...
Posted on November 20, 2014 at 11:52Issue #8 The USB host transactions fail (always) with transaction error interrupt when the core is in sleep mode. The USB device mode seems OK.
Posted on October 16, 2014 at 15:11 .ExternalClass9C006420E7B447A398C4A25B5B3E330E p {margin-bottom:0.1in;line-height:120%;} Issue #7talking about TxFifo's do you see something wrong in this code: USBx->GRSTCTL = ( USB_OTG_GRSTCTL_TXFFLSH |(uint3...
Posted on October 16, 2014 at 14:55 .ExternalClass30FCE68B09684A65A136EF83C82FEF2B p {margin-bottom:0.1in;line-height:120%;} Issue # 6Errata:OTG host blocks the receive channel when receiving IN packets and no TxFIFO is configuredI am quite confu...
Posted on October 16, 2014 at 14:14 .ExternalClass1E00B791F63449EF8045CAE6FC47773E p {margin-bottom:0.1in;line-height:120%;} About issue#4It seems CHENA and CHDIS are not exactly memory registers. I mean if you write “1�? to a register bit the wr...
