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PaulMoosman · 2023-10-20

We have Cortex-M7 STM32H7 (STM32H753) system and we are experiencing buffer underrun.We have read application note AN4861 which describes issues that can cause buffer underrun. I think we have implemented all the recommendations in AN4861, however, w...

PaulMoosman · 2023-11-14

@Piranha Thanks for your reply.We are currently only using 8MB of the FMC address space. We are only using 8MB of FMC SDRAM Bank #1. I created FMC MPU regions disabling access to regions we are not using. This seems to have fixed our LTDC fifo underr...

PaulMoosman · 2023-11-06

@Piranha Thanks for your response. I have read the application notes you mention and I have read the community post you reference. However, I will take another look at them and see if I missed anything.I configured the FMC and QuadSPI regions as stro...

PaulMoosman · 2023-11-06

@F.Belaid Thanks for your response.| You can monitor the bus activity and see which memory regions are being accessed when the buffer underrun occurs. This can help you identify any potential issues with speculative reads. How would I monitor the bus...

PaulMoosman · 2023-10-26

@FBL Thanks for your response.| You can monitor the bus activity and see which memory regions are being accessed when the buffer underrun occurs. This can help you identify any potential issues with speculative reads.How would I monitor the bus activ...

PaulMoosman · 2023-10-21

By buffer underrun, I'm referring to the LTDC global error interrupt "FIFO underrun". Pitch is the distance between the start of one line and the beginning of the next line in bytes in the framebuffer.

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STM32H7 buffer underrun and speculative reads

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