Posted on May 17, 2011 at 12:19Quote:With 0 wait-state, I have 0.70 DMips/MHz, which seems coherent (the drop with/without wait state seems reasonable). This was with arm-none-eabi-gcc v4.2.1. I have tested with v4.3.2 (the latest release) and get (...
Posted on May 17, 2011 at 12:19Quote:On 20-10-2008 at 17:57, Anonymous wrote: Hi, I think the means to achieve 1,25DMips/MHz is to operate the device at 48MHz with 0 wait states. In this case You achieve the highest DMips/MHz value but not the fast...
Posted on May 17, 2011 at 12:19Quote:On 20-10-2008 at 16:45, Anonymous wrote: Frank, The ACR is documented in the Flash programming manual. (13259.pdf) According to this, bit 4 in the ACR is the prefetch buffer enable bit. Obviously turning on the ...
Posted on May 17, 2011 at 12:19Quote:On 20-10-2008 at 11:05, Anonymous wrote: Hi Giovanni, What is the ACR register of the STM32? What STM32 did you use? I have benched the STM32F103RB (STM32 Primer) and adding 2 wait-state decrease significantly t...
Posted on May 17, 2011 at 12:19Hi Giovanni, What is the ACR register of the STM32? What STM32 did you use? I have benched the STM32F103RB (STM32 Primer) and adding 2 wait-state decrease significantly the performance. BTW, there is absolutely nothing...
