Trying to set the RCC_BDCR.BDRST bit before clock init makes the LSE hang on LSERDY bit.while rcc.bdcr.read().lserdy().bit_is_clear() {} If we try to init the HSE instead of LSE it hangs on HSI16match clock_source { ClockSource::L...

Hi again ;)Attaching clock configuration, can provide more info if needed. I also added the init of the periphs...Added the schematics for the clock HSE and LSE, and power inputs.We tested changing the IWDG timeout to random number eg. 6-10 sec. Then...

Hi @waclawek.jan I am a collegue of @hlanden The BOOT0 pin is pulled low with a 10kΩ,There are indication that the system is stuck at clock init and we are also calling a couple of statics (buffers) before WD is initialized but not sure if this has a...