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Hi,I'd like to report a bug in code generation of CubeMX when using encoder mode with remapping of CH1 and CH2 and LL drivers. I use STM32CubeIDE v1.4.1 and STM32G474.The problem is that the commands to configure the remapping of TI1 and TI2 are spli...
Hi,I'm trying to get the dual bank image swap feature of the STM32G4 to work, so far without success.I tried first on my own board by following the (very sparse) information in the reference manual. However every time I set the BFB2 bit in software a...
Hi,I have found a bug in the instructions order in code generated by STM32CubeIDE v1.3.0 for the IWDG (STM32G474) with LL drivers. The code itself pads the watchdog outside the acceptance window as soon as the window is set to a value sufficiently fa...
Hi,the meaning of the PLS[2:0] bits in the PWR_CR2 register is not yet documented in the RM0440 Rev2, they're marked "TBD" (see screenshot attached). Could you provide the mapping of thresholds levels?Thanks a lot!Regards,Matthias
Hello,I'm confused about the documentation of the (Re)Synchronization Jump Width SJW for FDCAN in the RM0440 of STM32G4. There is a difference in docu for valid values for SJW between section "43.3.1 Bit Timing": one to four quantasection "43.4.7 FDC...
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