About AGipe.1

AGipe.1 · 2020-02-06

I am looking at options to replace my mostly obsolete design using an FPGA and old linear CCDs. I've already chosen a new linear CCD chip but I'm considering a handful of processing options. Our CCD alignment system currently uses 13 bits output to o...

AGipe.1 · 2020-02-12

I'm not worried about the bit count. So in the picture above, our controller would read these bits right to left as they are streamed in. The final two bits (a 0 followed by a 1) are not part of the data count but are added by our FPGA as part of the...

AGipe.1 · 2020-02-07

See below for more info. I accidentally replied incorrectly I think. I'm new to the forums.

AGipe.1 · 2020-02-06

Synchronous. Clocks are currently generated from our FPGA, passed through a couple video driver ICs and load resistors mostly just to condition the pulse amplitude to what the CCD needs. Using a 20MHz crystal for master. See below for an example of t...

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I am trying to process video signal from a linear CCD, is it possible to add two stop bits to the end of the digital output signal?

Re: I am trying to process video signal from a linear CCD, is it possible to add two stop bits to the end of the digital output signal?

Re: I am trying to process video signal from a linear CCD, is it possible to add two stop bits to the end of the digital output signal?

Re: I am trying to process video signal from a linear CCD, is it possible to add two stop bits to the end of the digital output signal?