About bwang_bd

bwang_bd · 2014-02-28

Posted on February 28, 2014 at 16:10Hello Everyone,I'm using STM32F051xx to communicate with a SPI slave deivce. I found a problem that between two byte SPI clocks, there is a gap. And in the gap the state of MOSI line is always zero but is not the ...

bwang_bd · 2014-03-01

Posted on March 01, 2014 at 15:23Hi All,I have solved this problem. Before sending 0xFF, I set the Frame Format to SPI TI Mode in SPIx_CR2 register. Then pulling down CS line. At last, I set the Frame Format to SPI Motorola Mode. By this way, the la...

bwang_bd · 2014-02-28

Posted on March 01, 2014 at 02:56Hi Jack and sung.chen_chung,Thanks for your help. I'm sorry I didn't explain why the SPI slave deivce need the MOSI to keep the last bit value of previous sent byte. The reason is:The SPI slave has two SPI operation ...

bwang_bd · 2014-02-28

Posted on February 28, 2014 at 17:23Yes. I have set the leading edge to sample data lines (CPHA = 0) and set clock to low when idle (CPOL = 0). The slave device requires both CPHA and CPOL are equal to 0.Can the 2 bits setting lead the MOSI to be lo...

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STM32F051xx SPI problem

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