About TBran.15

TBran.15 · 2019-11-20

I have a problem accessing a SRAM connected via a 16bit databus to the FMC on an STM32F469. The processor is running 168MHz, and the FMC configuration is this: hsram1.Instance = FMC_NORSRAM_DEVICE; hsram1.Extended = FMC_NORSRAM_EXTENDED_DEVICE...

TBran.15 · 2019-10-08

On a STM32F469, when jumping from DFU bootloader to main image, I have seen that the RCC_AHB1ENR register is set to 0x0 and not 0x0010 0000 which it should be after a reset, according to the documentation. This causes the CCM RAM to be disabled.Accor...

TBran.15 · 2019-12-18

Just got confirmation from ST that the FMC in the F469 does have the same issue.Once again thank you the the help.

TBran.15 · 2019-11-22

Thanks.It sounds very much like the issue we are facing.I'll contact ST.

TBran.15 · 2019-11-22

The SRAM is a IS61WV204816BLL-10BLII have attached two dumps of the bus activity. I only had access to the lower 4 bit of address and data, and no access to the RAM chip select. The speed is at the limit of the bandwith of the analyzer, hence the sma...

TBran.15 · 2019-10-09

Thank you.Since the bootloader documentation states that all registers touched by the bootloader is set to default reset values before jumping to main image, it is a bug in the bootloader. If this, or other bootloaders, leave the processor in a diffe...

User statistics

User Activity

How is the FMC supposed to behave when a slow write to one address is followed by a read from another address?

Does STM32F469 bootloader correctly restore used registers to default reset values?

Re: How is the FMC supposed to behave when a slow write to one address is followed by a read from another address?

Re: How is the FMC supposed to behave when a slow write to one address is followed by a read from another address?

Re: How is the FMC supposed to behave when a slow write to one address is followed by a read from another address?

Re: Does STM32F469 bootloader correctly restore used registers to default reset values?