Posted on November 19, 2013 at 23:26 The original post was too long to process during our migration. Please click on the attachment to read the original post.
Posted on November 20, 2013 at 22:13
FWIW, here are some photos of the filter working. This was done mainly for my education and familiarization with the STM32 F0 discovery board.
http://imgur.com/a/2egIS
I think that the code...
Posted on November 20, 2013 at 22:09
FWIW, here are some photos of the filter working. This was done mainly for my education and familiarization with the STM32 F0 discovery board.
http://imgur.com/a/2egIS
I think that the code...
Posted on November 20, 2013 at 04:34Regarding the DMA pointer, I think it is more convoluted then that. The DMA_CNDTRx register counts down, indicating how many values are left to transfer, while the data in the circular buffer counts up (I think)....
Posted on November 20, 2013 at 04:27I thought that the maximum permitted ADC clock was 14 MHz, and the actual clock speed would depend on how it was configured. With a 48 MHz system clock, and /4 for the ADC clock, it ends up at 12 MHz, unless the ...
Posted on November 20, 2013 at 04:23EGADS! Thank you and your eagle eyes. I removed that extra ADC_ChannelConfig, and now all is well! That's what I get for a sloppy copy and paste job, now that seems obvious where the second ''mystery'' convers...
