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hendrik2 · 2013-11-29

Posted on November 29, 2013 at 11:53ES0104: STM32F101xC/D/E and STM32F103xC/D/E high-density device limitationsIn CD00197763 �2.13.1 it is statedClear ADDR by reading SR1 register followed by reading SR3SR3? Not SR2? I assume this is an erratum in t...

hendrik2 · 2013-11-29

Posted on November 29, 2013 at 12:06Update: the POS bit needed to be set, then it only nacks the 2nd byte as intended.I2C_NACKPositionConfig(I2C2, I2C_NACKPosition_Next);

hendrik2 · 2013-11-29

Posted on November 29, 2013 at 11:58 The reason I ask is because I get 2 bytes NACK'ed instead of just the last one. SR1Register = I2C2->SR1; // If ADDR is set, we cannot read SR2 without clearing ADDR and triggering the // continuat...

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Erratum in errata of STM32F101xC/D/E ?

Re: Erratum in errata of STM32F101xC/D/E ?

Re: Erratum in errata of STM32F101xC/D/E ?