Posted on May 17, 2011 at 12:47Quote:On 09-10-2008 at 13:57, Anonymous wrote: thanks for posting back, I'm glad the issue is gone. > Difference between -O0 and -O1 is also surprisingly high. -O0 is almost a silly 1-to-1 translation, it produces ho...
Posted on May 17, 2011 at 12:47Quote:On 07-10-2008 at 22:50, Anonymous wrote: clearing the bit at the end of the ISR can cause lost ints, but it could also cause double triggering of the ISR for each (non-lost) int event. this could happen because t...
Posted on May 17, 2011 at 12:47Quote:I don't remember the detailed semantics of the interrupt pending bits, but assuming simple semantics what you say might not be true. if you clear the pending bit towards the end of the ISR you might be clearing t...
Posted on May 17, 2011 at 12:47Quote:On 07-10-2008 at 11:18, Anonymous wrote: let me ask the obvious: you did remember to configure the clock at 72MHz, right? I can't think of anything but the ISR taking too long. what's your idle loop? I mean, what...
Posted on May 17, 2011 at 12:47Quote:On 06-10-2008 at 09:12, Anonymous wrote: it sounds like your interrupt service routine isn't having enough time to complete between timer interrupts when you increase the frequency. I had a little time to measure...
