Hello, everyone, Thank you so much for you time. I have a question for you. According to device reference manual RM0377 for STM32L0xx series, in chapter 7.3.3 Clock configuration register (RCC_CFGR), set PLLDIV[1:0] to 00 is not allowed. So how c...
Thank you so much for your reply. PLL is indeed turned off. I am curious about if I accidentally set those field to "not allowed" or "forbidden" value, what problem will it cause? Is it "unknown consequence"?
I saw that bit field VOS[1:0] of PWR_CR is also "forbidden" to set to 00, and it note that "bits are unchanged and keep the previous value, no voltage change occurs". Is that the same case for setting PLLDIV[1:0]?
