Yep, another excellent point. For me, the problem is bit-related. I suppose that makes it a little different from the OP. Haven't seen anything too suspicious on the o-scope when it comes to the clock. The usual culprit, from what I've heard, is...

Good suggestion, but it doesn't seem to make a difference. Looking at the SPI bus on a scope, it looks like the responses from the slave are shifted before entering the master. Looks more like a problem with the way that the master is sending data ...

Hello All,Looks like I'm not the only one that has has this problem. Has anyone solved this since it was originally posted? Switching to UART is definitely not a satisfactory answer and something that definitely isn't an option for my design.