Hi,We are using STEF 01 e-Fuse in our design. In that EN pin is controlling through an FPGA but its return path is not common to VCC and VOUT.Please let me know the design will work ?Below I have attached the design approach image.

Please let me know the power dissipation at 4A current and thermal input detailsMaximum thermal junction temperature (Tjmax)Case to junction thermal resistance (Rjc)board to junction thermal resistance (Rjb)