About patrislav

patrislav · 2019-05-09

Hi,I've an application where I'd like to use LSE in passive mode driven by a slow (1Hz) signal.When testing bypass mode LSE with slow clocks, I observed long delays between startup (cold start) and LSERDY being set by hardware. When measuring that de...

patrislav · 2019-04-30

Hi,is it possible to use the L4's LSE in bypass mode, driven by a 1Hz signal?I have a set of L4 chips on a bus and would like to feed them a 1Hz / PPS signal from a precise / temperature-compensated clock (and then use the LSE with /1 prescaler for t...

patrislav · 2018-11-26

Hi,I'm waiting for 1.4.0 due to lack of LL drivers in 1.3.0.According to the thread linked below, 1.4.0 was planned "beginning of 18Q4", is there a new roadmap or release date when we can expect it?Currently it's holding us back from using the H7 at ...

patrislav · 2018-10-17

HiI want to start using the MPU on STM32F7, however when I enable the MPU then unaligned accesses lead to a HardFault immediately.Code to reproduce the HardFault:static unsigned short foo[5] = { 0 }; memcpy(&foo[1], &foo[3], 4);I wrote a minimal Hard...

patrislav · 2018-10-16

Hi, I have following system:NUCLEO-F767ZI board (STM32F767ZI)Playing a waveform on DAC1, running it through a magic analog black-box, feeding it back to ADC1. Recording the signal on ADC1, stopping the transfer after one full buffer has been recorde...

patrislav · 2019-05-09

4 seconds at 1 KHz  where did you find 1KHz as minimum freq. for LSE?in STM32L431xx datasheet, it mentions no minimum limit for LSE freq. in bypass mode(page 115)

patrislav · 2019-04-30

Yeah, I got a bunch of nucleos lying around anyway, so I guess I'll just give it a try.

patrislav · 2018-10-18

Ok, after some further digging I got it!What I'm experiencing is the superposition of 2 problems.Problem 1)As soon as a memory region is set to bufferable and non-cacheable, it becomes a "device" region.And this means that every unaligned access rais...

patrislav · 2018-10-18

Hi @Bob S and @Community member , thank you for your comments.In an effort to further narrow this down and isolate it from any other stuff that might or might not have side effects, I created a new test, starting with an empty CubeMX project, using...

patrislav · 2018-10-17

@Bob S , I'm not reading past the end of the array, it's an array of unsigned shorts. so 4 bytes means 2 array elements, so foo[3] and foo[4] are copied. Anyway that code is just for illustration.Yes, in the meantime I extended my fault handler to r...

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LSERDY: long startup delay, when LSE in bypass mode driven by a slow clock

STM32L4 LSE 1Hz PPS

When will STM32CubeH7 1.4.0 be released?

HardFault on unaligned access, after enabling MPU

DMA RX buffer cache invalidation - BEFORE or AFTER a transfer?

Re: LSERDY: long startup delay, when LSE in bypass mode driven by a slow clock

Re: STM32L4 LSE 1Hz PPS

Re: HardFault on unaligned access, after enabling MPU

Re: HardFault on unaligned access, after enabling MPU

Re: HardFault on unaligned access, after enabling MPU