About mhaun

mhaun · 2017-07-06

Posted on July 07, 2017 at 05:45For a while now, I've been wanting to learn the DFSDM (cascaded-integrator-comb, or CIC, filter) peripheral on the STM32L4 and use it for some serious DSP work. This week I finally had time to dig in and get it worki...

mhaun · 2017-04-18

Posted on April 18, 2017 at 20:28AN4621 'STM32L4 ultra-low-power features overview' says (page 16):The STM32L4A6xG, thanks to the external SMPS supply option, makes it possible to force on the Vcore pins (when the MR is in use) an external VDD12 sup...

mhaun · 2016-03-22

Posted on March 22, 2016 at 20:10I'd like to use an STM32L4 in a project where I am interfacing with a 1-MSPS, 16-bit SPI ADC (LTC2378-16). Obviously the SPI clock has to be > 16 MHz to run this at full speed. However, for best performance the clo...

mhaun · 2016-03-03

Posted on March 03, 2016 at 23:36On STM32L4 (and some other parts), the FB_MODE bit in SYSCFG->MEMRMP is used to swap the mapping of flash banks 1 and 2. This is how the factory bootloader implements ''boot from bank 2'' (BFB2) in the flash option ...

mhaun · 2016-02-23

Posted on February 23, 2016 at 18:15I've recently delved into this subject because I need to design a firmware upgrade mechanism on the STM32L4xx. The documentation is pretty much useless, as it is not only incomplete, but contradictory too. I'm g...

mhaun · 2017-07-07

Posted on July 07, 2017 at 19:48Thanks Jan,You are correct. I have some familiarity with CIC filters, but I did not remember that the required width of each integrator/comb stage matches the required width at the filter output, prior to the barrel ...

mhaun · 2017-04-18

Posted on April 18, 2017 at 23:50Fascinating. So the STM32L4A6xx datasheet does not have this (the P option in the part-numbering table), even though AN4621 claims that the VDD12 pin is *only* available on the STM32L4A6 devices, and not on any othe...

mhaun · 2016-03-23

Posted on March 23, 2016 at 16:33So the MOSI inputs (in slave mode) and MISO inputs (in master mode) may have differences inside the peripheral... could be I suppose. It would be useful to hear from anyone who has pushed the chip to its limits and ...

mhaun · 2016-03-15

Posted on March 16, 2016 at 00:30Confirmed. For MER1/MER2 purposes, ''bank 1'' always refers to the same bank and ''bank 2'' always refers to the same bank.

mhaun · 2016-02-24

Posted on February 24, 2016 at 18:02Thanks Clive, I finally discovered the FB_MODE bit in SYSCFG. Presumably that bit is toggled by the rom bootloader based on its reading of BFB2 and sanity checking the initial SP. This is starting to make sense....

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DFSDM limited dynamic range at high F_OSR?

External switching power supply support still planned for STM32L4?

Confused by STM32L4 datasheet max SPI clock frequencies

Flash mass erase: are MER1/MER2 bits swapped when flash banks are swapped?

BFB2 and bootloader flash-bank selection

Re: DFSDM limited dynamic range at high F_OSR?

Re: External switching power supply support still planned for STM32L4?

Re: Confused by STM32L4 datasheet max SPI clock frequencies

Re: Flash mass erase: are MER1/MER2 bits swapped when flash banks are swapped?

Re: BFB2 and bootloader flash-bank selection